Electrode contacts

Patent metadata

Field	Value
Publication number	US-9502653-B2
Application number	US-201414581193-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 25, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A device structure providing contact to conductive layers via a deep trench structure is disclosed. The device includes a first dielectric layer including a first opening. A first conductive layer is deposited over the first dielectric layer and the first opening. A second dielectric layer is deposited on the first conductive layer. The second dielectric layer includes a second opening. A second conductive layer is deposited over the second dielectric layer and the first and second openings. A semiconductor layer is deposited on the second dielectric layer such that the semiconductor layer is not continuous on at least part of the walls of the first or second openings. A top electrode layer is deposited on the semiconductor layer. The top electrode layer is in contact with the second conductive layer on at least part of the walls of the first or second openings.

First claim

What is claimed is:

1. A device structure providing contact to conductive layers via a deep trench structure, the device structure comprising:
a first dielectric layer including a flat top surface around a first opening, the first opening having walls on the first dielectric layer;
a first conductive layer deposited over the flat top surface and the first opening of the first dielectric layer;
a second dielectric layer deposited on the first conductive layer, the second dielectric layer including a flat top surface around a second opening having walls on the second dielectric layer, wherein the first conductive layer is located between the first and second dielectric layer;
a second conductive layer deposited over the second dielectric layer and the first and second openings;
a semiconductor layer deposited on the second conductive layer, the semiconductor layer being continuous on the flat top surface of the first and second dielectric layers, the semiconductor layer continuously covering a lower portion of the walls of the first and second openings, and being discontinuous on an upper portion of the walls between the lower portion of the walls and the flat top surfaces; and
a top electrode layer deposited on the semiconductor layer, the top electrode layer in contact with the second conductive layer on the upper portion of the walls of the first or second openings.

2. The device structure of claim 1 , wherein the first and second openings are created by one of lithography, liftoff, molding or shadow masking.

3. The device structure of claim 1 , wherein the semiconductor layer is an organic light emitting diode.

4. The device structure of claim 1 , wherein the first dielectric layer is silicon-nitride and the second dielectric layer is a polymer.

5. The device structure of claim 1 , wherein the first and second dielectric layers, the first and second conductive layers and the semiconductor layer are deposited via at least one of PECVD, CVD, sputtering, vapor deposition, printing, spin coating, and spray coating.

6. A method of fabricating a device structure providing contact to conductive layers via a deep trench structure, the method comprising:
depositing a first dielectric layer having a flat top surface;
creating a first opening in the flat top surface of the first dielectric layer, the first opening having walls on the first dielectric layer;
depositing a first conductive layer over the flat top surface and the first opening of the first dielectric layer;
depositing a second dielectric layer having a flat top surface on the first conductive layer;
creating a second opening on the flat top surface of the second dielectric layer, the second opening having walls on the second dielectric layer, and wherein the first conductive layer is located between the first and second dielectric layers;
depositing a second conductive layer over the second dielectric layer and the first and second openings;
depositing a semiconductor layer on the second conductive layer, the semiconductor layer being continuous on the flat top surface of the first and second dielectric layers, the semiconductor layer continuously covering a lower portion of the walls of the first and second openings, and being discontinuous on an upper portion of the walls between the lower portion of the walls and the flat top surfaces; and
depositing a top electrode layer on the semiconductor layer, the top electrode in contact with the second conductive layer on the upper portion of the walls of the first or second opening.

7. The method of claim 6 , wherein the first and second openings are created by one of lithography, liftoff, molding or shadow masking.

8. The method of claim 6 , wherein the semiconductor layer is an organic light emitting diode.

9. The method of claim 6 , wherein the first dielectric layer is silicon-nitride and the second dielectric layer is a polymer.

10. The method of claim 6 , wherein the first and second dielectric layers, the first and second conductive layers and the semiconductor layer are deposited via at least one of PECVD, CVD, sputtering, vapor deposition, printing, spin coating, and spray coating.

11. A device structure providing contact to conductive layers via a deep trench structure, the device structure comprising:
a first dielectric layer including a top surface and a side wall;
a first conductive layer deposited over the first dielectric layer on the top surface and the side wall;
a second dielectric layer deposited on the first conductive layer, the second dielectric layer including a top surface and a side wall;
a second conductive layer having a portion deposited over the top surface of the second dielectric layer and a portion deposited on the side wall of the second dielectric layer and the first conductive layer;
a semiconductor layer having a portion deposited on the portion of the second conductive layer deposited over the top surface of the second dielectric layer, and a continuous portion deposited on the portion of the second conductive layer deposited on a lower portion of the side wall of the second dielectric layer and the first conductive layer, the semiconductor layer being discontinuous over the portion of the second conductive layer deposited on an upper portion of the side wall between the lower portion of the side wall and the top surface; and
a top electrode layer deposited on the semiconductor layer, the top electrode layer in contact with the second conductive layer on the upper portion deposited on the side wall of the second dielectric layer and the top electrode layer being in contact with the second conductive layer on the first conductive layer on the upper portion of the side wall of the first dielectric layer.

12. The device structure of claim 11 , wherein the side walls of the first and second dielectric layers are created by one of lithography, liftoff, molding or shadow masking.

13. The device structure of claim 11 , wherein the semiconductor layer is an organic light emitting diode.

14. The device structure of claim 11 , wherein the first dielectric layer is silicon-nitride and the second dielectric layer is a polymer.

15. The device structure of claim 11 , wherein the first and second dielectric layers, the first and second conductive layers and the semiconductor layer are deposited via at least one of PECVD, CVD, sputtering, vapor deposition, printing, spin coating, and spray coating.

16. The device structure of claim 11 , wherein the side walls of the first and second dielectric layers are positioned at a predetermined angle relative to the respective top surfaces.

17. The device structure of claim 11 , wherein the first conductive layer is a backplane for the device structure.

18. The device structure of claim 11 , wherein the second conductive layer is a low resistance conductor and the top electrode layer is a high resistance conductor.

19. The device structure of claim 11 , wherein the top electrode layer is transparent.

Assignees

• Ignis Innovation Inc

Inventors

• Chaji Gholamreza

Classifications

• H10K50/814

  combined with auxiliary electrodes, e.g. ITO layer combined with metal lines · CPC title

• H10K71/60 Primary

  Forming conductive regions or layers, e.g. electrodes · CPC title

• H01L51/0021 Primary

  Electricity · mapped topic

• H01L27/3248

  Electricity · mapped topic

• H10K50/822

  characterised by their shape · CPC title