Methods for passivating a carbonic nanolayer
US-2015064886-A1 · Mar 5, 2015 · US
Resistive random-access memory (RRAM) with a low-K porous layer
US9502647B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502647-B2 |
| Application number | US-201414288688-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 28, 2014 |
| Priority date | May 28, 2014 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a resistance-switching network disposed between the pair of electrodes. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer. The group-IV doping layer comprises silicon oxide doped with a group-IV element. The porous low-k layer comprises porous silicon oxide or porous hafnium oxide. The group-IV element may comprise zirconium, titanium, or hafnium. The porous low-k layer may be prepared by inductively coupled plasma (ICP) treatment. A method of fabricating a resistive memory is disclosed. The method comprises forming a resistance-switching network on a first electrode using sputtering and forming a second electrode on the resistance-switching network using sputtering. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of fabricating a resistive memory, comprising: forming a first conductive film as a first electrode; forming a group-IV element, a dielectric material, and a porous low-k layer together using sputtering to form a resistance-switching network on the first electrode, wherein forming the group-IV element, the dielectric material, and the porous low-k layer together using sputtering comprises forming the porous low-k layer using inductively coupled plasm…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9502647B2 cover?
- A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a resistance-switching network disposed between the pair of electrodes. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer. The group-IV doping layer comprises silicon oxide doped with a group-IV element. The porous low-k layer comprises porous sili…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H01L45/1233. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).