Semiconductor device, magnetic memory device, and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9502643-B2
Application number	US-201514606157-A
Country	US
Kind code	B2
Filing date	Jan 27, 2015
Priority date	Apr 28, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A method of fabricating a semiconductor device includes forming conductive pillars on a substrate, sequentially forming a sacrificial layer and a molding structure between the conductive pillars, forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars, removing the sacrificial layer to form an air gap, removing the molding structure to form an expanded air gap, and patterning the conductive layer to open the expanded air gap.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
forming conductive pillars on a substrate;
sequentially forming a sacrificial layer and a molding structure between the conductive pillars;
forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars;
removing the sacrificial layer to form an air gap;
removing the molding structure to form an expanded air gap; and
patterning the conductive layer to open the expanded air gap.

2. The method as claimed in claim 1 , wherein:
the substrate includes a cell array region and a peripheral circuit region, and
removing the molding structure is performed through a pathway that is located between the cell array region and the peripheral circuit region.

3. The method as claimed in claim 2 , wherein the cell array region has first to fourth edges adjacent to the peripheral circuit region, and the pathway is formed to cross at least one of the first to fourth edges.

4. The method as claimed in claim 2 , wherein removing the molding structure is performed after the forming of the conductive layer.

5. The method as claimed in claim 2 , wherein removing the molding structure includes:
forming a mask pattern to cover the cell array region and expose the peripheral circuit region;
performing a patterning process using the mask pattern as an etch mask to expose a sidewall of the molding structure, and
etching the molding structure exposed by the patterning process.

6. The method as claimed in claim 5 , wherein:
removing the sacrificial layer is performed after forming of the conductive layer and after the patterning process, the patterning process being performed to expose the sacrificial layer, and
etching the molding structure is performed after removing the sacrificial layer.

7. The method as claimed in claim 6 , wherein:
the patterning process is performed to expose a sidewall of the conductive layer, and
the method further comprises forming a spacer insulating layer on the sidewall of the conductive layer exposed by the patterning process to seal the air gap, after removing the sacrificial layer.

8. The method as claimed in claim 6 , wherein:
the patterning process is performed to expose a sidewall of the conductive layer, and
the method further comprises performing a thermal oxidation process to form a capping oxide layer on the exposed sidewall of the conductive layer, before removing the sacrificial layer.

9. The method as claimed in claim 5 , wherein:
removing the sacrificial layer is performed before forming the conductive layer,
removing the molding structure is performed after removing the sacrificial layer, and
the patterning process is performed to open the air gap.

10. The method as claimed in claim 9 , wherein:
forming the molding structure includes forming first molding patterns on upper sidewalls of the conductive pillars, and
the sacrificial layer is removed through gap regions between the first molding patterns.

11. The method as claimed in claim 10 , wherein the first molding patterns are formed using a spacer process to have a ring-shaped structure enclosing the upper sidewall of the conductive pillar, when viewed in a plan view.

12. The method as claimed in claim 10 , wherein the first molding patterns are formed to have penetrating holes exposing the sacrificial layer.

13. The method as claimed in claim 1 , wherein:
the conductive layer includes a lower electrode layer and a magnetic tunnel junction layer on the lower electrode layer,
the lower electrode layer is formed before removing the molding structure, and
the magnetic tunnel junction layer is formed after removing the molding structure.

14. A method of fabricating a magnetic memory device, the method comprising:
preparing a substrate with a cell array region and a peripheral circuit region;
forming conductive pillars on the cell array region;
sequentially forming a sacrificial layer and a molding structure on the conductive pillars;
forming a conductive layer on the molding structure;
removing the sacrificial layer to form an air gap between the conductive pillars;
performing a first patterning process using a mask pattern covering the cell array region and exposing the peripheral circuit region to expose the molding structure;
removing the molding structure exposed through a boundary between the cell array region and the peripheral circuit region to form an expanded air gap; and
performing a second patterning process on the conductive layer to open the expanded air gap.

15. The method as claimed in claim 14 , wherein:
the first patterning process is performed to expose the sacrificial layer, and
removing the sacrificial layer is performed through a pathway that is located between the cell array region and the peripheral circuit region, after the first patterning process.

16. The method as claimed in claim 15 , wherein;
the first patterning process is performed to expose a sidewall of the conductive layer, and
the method further comprises performing a thermal oxidation process to form a capping oxide layer on the exposed sidewall of the conductive layer.

17. The method as claimed in claim 15 , wherein:
the first patterning process is performed to expose a sidewall of the conductive layer, and
the method further comprises forming a spacer insulating layer to seal the air gap, before removing the molding structure.

18. The method as claimed in claim 14 , wherein:
removing the sacrificial layer is performed before forming the conductive layer,
removing the molding structure is performed after removing the sacrificial layer, and
the first patterning process is performed to open the air gap.

19. The method as claimed in claim 14 , wherein:
forming the conductive layer includes sequentially forming a lower electrode layer and a magnetic tunnel junction layer on the molding structure,
the lower electrode layer is formed before removing the molding structure, and
the magnetic tunnel junction layer is formed after removing the molding structure.

20. A method of fabricating a semiconductor device, the method comprising:
forming conductive pillars on a substrate;
sequentially forming a sacrificial layer and a molding structure between the conductive pillars;
forming a conductive layer on the molding structure, such that the conductive layer is connected to the conductive pillars;
removing the sacrificial layer, such that an air gap is formed between adjacent conductive pillars;
removing the molding structure, such that an expanded air gap is formed between the adjacent conductive pillars; and
patterning the conductive layer to form conductive patterns on respective conductive pillars, such that a space between the conductive patterns is in fluid communication with the expanded air gap.

Assignees

• Bae Byoungjae
• Park Jongchul
• Kwon Shin
• Kim Inho
• Sun Changwoo
• Samsung Electronics Co Ltd

Inventors

• Bae Byoungjae
• Park Jongchul
• Kwon Shin
• Kim Inho
• Sun Changwoo

Classifications

• H01L43/08

  Electricity · mapped topic

• H01L27/228

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic

• H10N50/10

  Magnetoresistive devices · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title