Array substrate and manufacturing method thereof
US-12185597-B2 · Dec 31, 2024 · US
Backplane for flat panel display apparatus, method of manufacturing the backplane, and organic light emitting display apparatus including the backplane
US9502604B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502604-B2 |
| Application number | US-201514810179-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 27, 2015 |
| Priority date | Apr 12, 2012 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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Abstract
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A backplane for a flat panel display apparatus, includes: a thin film transistor (TFT) on a substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode; a light-blocking layer between the substrate and the TFT; a first insulating layer between the light-blocking layer and the TFT; a capacitor including a first electrode on the same plane as the light-blocking layer, and a second electrode on the first electrode, wherein the first insulating layer is between the first electrode and the second electrode; and a pixel electrode on the same plane as the light-blocking layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A backplane comprising: a substrate; a thin film transistor (TFT) on the substrate and the TFT comprising: an active layer comprising oxygen (O) and at least one element selected from the group consisting of gallium (Ga), indium (In), zinc (Zn), hafnium (Hf), and tin (Sn), wherein the active layer comprises a channel region and a source region and a drain region with ion impurities which are disposed outside the channel region; a gate electrode on the a…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9502604B2 cover?
- A backplane for a flat panel display apparatus, includes: a thin film transistor (TFT) on a substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode; a light-blocking layer between the substrate and the TFT; a first insulating layer between the light-blocking layer and the TFT; a capacitor including a first electrode on the same plane as the light-blo…
- Who is the assignee on this patent?
- Samsung Display Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6723. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).