Wafer processing apparatus and wafer processing method
US-2024395512-A1 · Nov 28, 2024 · US
US9502571B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502571-B2 |
| Application number | US-201314361131-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 19, 2013 |
| Priority date | Apr 11, 2013 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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A thin film layer and manufacturing method thereof, a substrate for display and a liquid crystal display are provided. The embodiments according to the present invention can solve the problem that the gradient at the edge of the thin film layer produced with current methods is too steep or perpendicular, thus the thin film layer deposited in the next step easily has step coverage defect or even breakage. The thin film layer of the embodiments of the present invention comprises a plurality of sub-layers with different densities, wherein, the density of an upper sub-layer is smaller than that of a lower sub-layer. The yield and reliability of the thin film transistor and the thin film transistor liquid crystal display produced with the thin film layer of the embodiments of the present invention are high.
Opening claim text (preview).
The invention claimed is: 1. A thin film layer, comprising a plurality of sub-layers with different densities, wherein, an upper sub-layer has a density smaller than that of a lower sub-layer, and the thin film layer is at least one of an active layer and a source/drain electrode layer, and wherein the thin film layer is any of an aluminum layer, a copper layer, an indium tin oxide layer, and a zinc oxide layer. 2. The thin film layer according to claim 1 , whe…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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