Non-planar quantum well device having interfacial layer and method of forming same

Patent metadata

Field	Value
Publication number	US-9502568-B2
Application number	US-201514804019-A
Country	US
Kind code	B2
Filing date	Jul 20, 2015
Priority date	Sep 24, 2010
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

First claim

What is claimed is:

1. A system comprising:
a memory;
at least one of a processor and a controller coupled to the memory; and
a non-planar quantum well device comprising:
a quantum well structure comprising a quantum well layer and at least one of a IV and III-V material barrier layer, the quantum well layer including a channel region;
a fin structure (a) in the quantum well structure, and (b) including the quantum well layer;
a high-k layer over the fin structure; and
a gate metal over the high-k layer.

2. The system of claim 1 comprising an interfacial layer over the fin structure; wherein (a) the interfacial layer comprises epitaxial silicon, and (b) the quantum well structure includes an intermediate layer, between the interfacial layer and the high-k layer, which comprises silicon dioxide.

3. The system of claim 1 , wherein the memory includes the quantum well structure.

4. The system of claim 1 , wherein the at least one of a processor and a controller includes the processor and the processor includes the quantum well structure.

5. The system of claim 1 , wherein the at least one of a processor and a controller includes the controller and the controller includes the quantum well structure.

6. The system of claim 1 , wherein the at least one of a processor and a controller includes the quantum well structure and the memory includes an additional quantum well structure, the additional quantum well structure comprising:
an additional quantum well layer and an additional at least one of a IV and III-V material barrier layer, the additional quantum well layer including an additional channel region;
an additional fin structure (a) in the additional quantum well structure, and (b) including the additional quantum well layer;
an additional high-k layer over the additional fin structure; and
an additional gate metal over the additional high-k layer.

7. The system of claim 1 , wherein the quantum well layer includes germanium.

8. The system of claim 1 comprising an intermediate layer between an interfacial layer and the high-k layer.

9. The system of claim 8 , wherein the intermediate layer comprises a dielectric material different from a material of the high-k layer.

10. The system of claim 8 , wherein the intermediate layer comprises at least one of silicon dioxide, alumina, zirconia and hafnium silicate.

11. The device of claim 8 , wherein the intermediate layer includes a material obtained from an oxidization of a surface of the interfacial layer.

12. The system of claim 1 comprising an interfacial layer that covers a 100 surface and a 110 surface of the fin structure.

13. The system of claim 1 comprising an interfacial layer, over the fin structure, which comprises silicon.

14. The system of claim 13 , wherein the silicon is epitaxial.

15. The system of claim 1 comprising an interfacial layer, over the fin structure, which comprises a single monolayer of atoms.

16. The system of claim 1 comprising drain and source regions at respective ends of the fin structure.

17. The system of claim 1 , wherein the quantum well structure includes a doping layer.

18. The system of claim 1 , wherein the quantum well layer is epitaxial.

19. A system comprising:
a memory comprising a non-planar quantum well device that includes:
a quantum well structure having a quantum well layer and at least one of a IV and III-V material barrier layer, the quantum well layer including a channel region;
a fin structure (a) formed in the quantum well structure and, (b) including the quantum well layer; and
a high-k layer and a gate material both provided over the fin structure.

20. A system comprising:
at least one of a processor and a controller comprising a non-planar quantum well device that includes:
a quantum well structure having a quantum well layer and at least one of a IV and III-V material barrier layer, the quantum well layer including a channel region;
a fin structure (a) formed in the quantum well structure and, (b) including the quantum well layer; and
a high-k layer and a gate material both provided over the fin structure.

Assignees

• Intel Corp

Inventors

• Rachmady Willy
• Pillarisetty Ravi
• Le Van H
• Chau Robert S

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title