Semiconductor device
US-12057459-B2 · Aug 6, 2024 · US
US9502448B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502448-B2 |
| Application number | US-201514934864-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 6, 2015 |
| Priority date | Nov 26, 2012 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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Official abstract text for this publication.
A method for fabricating an array substrate includes sequentially forming a bottom gate, a first gate insulating layer, an active layer and a second gate insulating layer on a base substrate, a gate line being formed at the same time as forming the bottom gate; forming a top gate on the second gate insulating layer; sequentially forming a gate isolation layer, a source electrode, a drain electrode and a pixel electrode on the top gate. Before forming the top gate on the second gate insulating layer, the method includes forming a nickel layer at an area on the active layer where the source electrode is to be formed and/or an area on the active layer where the drain electrode is to be formed, and then performing a heat treatment on the active layer at a temperature in the range of 500° C.-570° C. for 2 hours in an atmosphere of H2.
Opening claim text (preview).
The invention claimed is: 1. A method for fabricating an array substrate, including steps: S1: sequentially forming a bottom gate, a first gate insulating layer, an active layer and a second gate insulating layer on a base substrate, wherein a gate line is formed at the same time as forming the bottom gate; S2: forming a top gate on the second gate insulating layer; S3: sequentially forming a gate isolation layer, a source electrode, a drain electrode and a pixel electrode on…
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