Method for fabricating an array substrate with improved driving ability

US9502448B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9502448-B2
Application numberUS-201514934864-A
CountryUS
Kind codeB2
Filing dateNov 6, 2015
Priority dateNov 26, 2012
Publication dateNov 22, 2016
Grant dateNov 22, 2016

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Abstract

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A method for fabricating an array substrate includes sequentially forming a bottom gate, a first gate insulating layer, an active layer and a second gate insulating layer on a base substrate, a gate line being formed at the same time as forming the bottom gate; forming a top gate on the second gate insulating layer; sequentially forming a gate isolation layer, a source electrode, a drain electrode and a pixel electrode on the top gate. Before forming the top gate on the second gate insulating layer, the method includes forming a nickel layer at an area on the active layer where the source electrode is to be formed and/or an area on the active layer where the drain electrode is to be formed, and then performing a heat treatment on the active layer at a temperature in the range of 500° C.-570° C. for 2 hours in an atmosphere of H2.

First claim

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The invention claimed is: 1. A method for fabricating an array substrate, including steps: S1: sequentially forming a bottom gate, a first gate insulating layer, an active layer and a second gate insulating layer on a base substrate, wherein a gate line is formed at the same time as forming the bottom gate; S2: forming a top gate on the second gate insulating layer; S3: sequentially forming a gate isolation layer, a source electrode, a drain electrode and a pixel electrode on…

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What does patent US9502448B2 cover?
A method for fabricating an array substrate includes sequentially forming a bottom gate, a first gate insulating layer, an active layer and a second gate insulating layer on a base substrate, a gate line being formed at the same time as forming the bottom gate; forming a top gate on the second gate insulating layer; sequentially forming a gate isolation layer, a source electrode, a drain electr…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D30/6734. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).