Array substrate and manufacturing method thereof
US-2024038786-A1 · Feb 1, 2024 · US
Array substrate and manufacturing method thereof, display device
US9502447B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502447-B2 |
| Application number | US-201314358444-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 13, 2013 |
| Priority date | Aug 27, 2013 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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Abstract
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An array substrate comprises a base substrate, a gate line, a data line and a thin film transistor arranged in an array on the base substrate, a pixel electrode and a passivation layer, the thin film transistor include a gate electrode, an active layer, a source electrode and a drain electrode, and the pixel electrode and the active layer, the drain are disposed in a same layer and formed integrally. A display device comprising the array substrate and a manufacturing method of the array substrate are further disclosed.
First claim
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The invention claimed is: 1. An array substrate comprising a base substrate, a gate line, a data line and a thin film transistor arranged in an array on the base substrate, a pixel electrode and a passivation layer, the thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode, wherein the pixel electrode and the active layer, the drain electrode are disposed in a same layer and formed integrally, the thin film transistor is a to…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9502447B2 cover?
- An array substrate comprises a base substrate, a gate line, a data line and a thin film transistor arranged in an array on the base substrate, a pixel electrode and a passivation layer, the thin film transistor include a gate electrode, an active layer, a source electrode and a drain electrode, and the pixel electrode and the active layer, the drain are disposed in a same layer and formed integ…
- Who is the assignee on this patent?
- Boe Technology Group Co Ltd, Boe Tech Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D86/0221. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).