Array substrate and manufacturing method thereof
US-12185597-B2 · Dec 31, 2024 · US
Thin film transistor array substrate and method of manufacturing the same
US9502445B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502445-B2 |
| Application number | US-201514809372-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 27, 2015 |
| Priority date | Sep 12, 2008 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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Abstract
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A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A thin film transistor array substrate comprising: a semiconductive oxide layer on an insulating substrate and including a channel portion; a gate electrode overlapping the semiconductive oxide layer; a first insulating layer between the semiconductive oxide layer and the gate electrode; and a second insulating layer disposed opposite to the first insulating layer with respect to the semiconductive oxide layer, wherein each of the first and second in…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9502445B2 cover?
- A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of th…
- Who is the assignee on this patent?
- Samsung Display Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D86/60. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).