Array substrate with connecting leads and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9502441-B2
Application number	US-201414406950-A
Country	US
Kind code	B2
Filing date	May 27, 2014
Priority date	Dec 18, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

An array substrate with connecting leads and a manufacturing method thereof are provided. The array substrate includes a substrate; a plurality of signal lines formed of a metal layer, which are disconnected at a cut zone of the substrate; a plurality of connecting leads disposed in an adjacent layer of the signal lines, which correspond to locations of the signal lines where they are disconnected, and directly contact with the signal lines; wherein, two ends of each of the signal lines in its disconnected position are electrically joined by the connecting leads, and the signal lines include gate lines, the connecting leads include first leads; wherein, the first leads are formed on the substrate, and the gate lines are located in an upper level than the first leads.

First claim

The invention claimed is:

1. An array substrate, comprising:
a substrate;
a plurality of signal lines formed of a metal layer, which are disconnected at a cut zone of the substrate;
a plurality of connecting leads disposed in an adjacent layer of the signal lines, which correspond to locations of the signal lines where they are disconnected, and directly contact with the signal lines;
wherein, two ends of each of the signal lines in its disconnected position are electrically joined by the connecting leads, and
the signal lines include gate lines, the connecting leads include first leads;
wherein, the first leads are formed on the substrate, and the gate lines are located in an upper level than the first leads.

2. The array substrate according to claim 1 , wherein, the signal lines further include data lines, the connecting leads further include second leads;
structure of the array substrate further includes a gate insulating layer, the second leads are formed on the gate insulating layer, and the data lines are located in an upper level than the second leads.

3. The array substrate according to claim 1 , wherein, the signal lines include gate lines, the connecting leads include first leads;
structure of the array substrate further includes a gate insulating layer, the first leads are formed on the gate insulating layer, and the gate lines are located in an upper level than the first leads.

4. The array substrate according to claim 3 , wherein, the signal lines further include data lines, the connecting leads further include second leads;
wherein, the second leads are formed on the substrate, the data lines are located in an upper level than the second leads, and the gate insulating layer is formed on the data lines.

5. The array substrate according to claim 1 , wherein, it further includes a plurality of common electrodes, and the first leads and the common electrodes are provided on a same layer.

6. The array substrate according to claim 1 , wherein, material for the connecting leads is a conductive oxide.

7. The array substrate according to claim 6 , wherein, material for the connecting leads is indium tin oxide, indium zinc oxide or aluminum zinc oxide.

8. The array substrate according to claim 3 , wherein, it further includes a plurality of common electrodes, and the first leads and the common electrodes are provided on a same layer.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Hu Haichen
• Xi Yusheng
• Liu Jiarong

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/0212

  comprising manufacture, treatment or coating of substrates · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title