Switching element with a series-connected junction FET (JFET) and MOSFET achieving both improved withstand voltage and reduced on-resistance

Patent metadata

Field	Value
Publication number	US-9502388-B2
Application number	US-201615017666-A
Country	US
Kind code	B2
Filing date	Feb 7, 2016
Priority date	Sep 30, 2011
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP 1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a first metal plate having a first surface and a second surface opposite to the first surface;
a second metal plate having a third surface and a fourth surface opposite to the third surface;
a first semiconductor chip mounted over the first surface of the first metal plate;
a second semiconductor chip mounted over the third surface of the second metal plate;
a first lead;
a second lead;
a third lead connected to the first metal plate; and
a sealing body sealing the first semiconductor chip, the second semiconductor chip, a part of the first lead, a part of the second lead, and a part of the third lead,
wherein the first semiconductor chip includes a junction FET (Field Effect Transistor) of a normally-on-type, which is formed with silicon carbide, and having a first gate electrode, a first source and a first drain,
wherein the first semiconductor chip has a first front surface on which a first source pad electrically connected with the first source of the junction FET and a first gate pad electrically connected with the first gate electrode of the junction FET are formed, and a first back surface electrically connected with the first drain of the junction FET and opposite to the first front surface,
wherein the second semiconductor chip includes a MOSFET (Metal Oxide Semiconductor FET) of a normally-off-type, which is formed with silicon, and having a second gate electrode, a second source and a second drain,
wherein the second semiconductor chip has a second front surface on which a second source pad electrically connected with the second source of the MOSFET and a second gate pad electrically connected with the second gate electrode of the MOSFET are formed, and a second back surface electrically connected with the second drain of the MOSFET and opposite to the second front surface,
wherein the first semiconductor chip is mounted over the first surface of the first metal plate via a first conductive adhesive material such that the first back surface of the first semiconductor chip faces the first surface of the first metal plate,
wherein the first drain of the junction FET is electrically connected with the third lead,
wherein the second semiconductor chip is mounted over the third surface of the second metal plate via a second conductive adhesive material such that the second back surface of the second semiconductor chip faces the third surface of the second metal plate,
wherein the second drain of the MOSFET is electrically connected with the second metal plate,
wherein the first gate pad of the first semiconductor chip is electrically connected with the first lead via a first wire,
wherein the second source pad of the second semiconductor chip is electrically connected with the first lead via a second wire,
wherein the second gate pad of the second semiconductor chip is electrically connected with the second lead via a third wire,
wherein the first source pad of the first semiconductor chip is electrically connected with the second metal plate via a fourth wire, and
wherein, in plan view, the first gate pad of the first semiconductor chip is arranged closer to the first lead than to the second and third leads.

2. The semiconductor device according to claim 1 ,
wherein the sealing body is of a quadrangular shape having a first side surface and a second side surface opposite to the first side surface, and
wherein a part of each of the first, second and third leads, which is exposed from the sealing body, is protruded from the first side surface.

3. The semiconductor device according to claim 2 ,
wherein the second surface of the first metal plate and the fourth surface of the second metal plate are covered with the sealing body.

4. The semiconductor device according to claim 2 ,
wherein a part of the sealing body is located between the first metal plate and the second metal plate.

Assignees

• Renesas Electronics Corp

Inventors

• Kanazawa Takamitsu
• Akiyama Satoru

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/762

  between stacked chips · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title