Printed circuit boards having blind vias, method of testing electric current flowing through blind via thereof and method of manufacturing semiconductor packages including the same

Patent metadata

Field	Value
Publication number	US-9502378-B1
Application number	US-201514938322-A
Country	US
Kind code	B1
Filing date	Nov 11, 2015
Priority date	May 29, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A method of manufacturing a semiconductor package is provided. The method includes providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer. Semiconductor chips are disposed on the plurality of unit substrate regions, respectively. Conductive wires are formed to electrically connect connection pads disposed on the plurality of unit substrate regions to bonding pads disposed on the semiconductor chips. The connection pads are electrically connected to the blind vias, and forming the conductive wires includes performing a test for confirming a current that flows between each conductive wire and the peripheral conductive pattern layer through the unit substrate region.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor package, the method comprising:
providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer;
mounting semiconductor chips on the plurality of unit substrate regions; and
forming conductive wires electrically connecting connection pads disposed on the plurality of unit substrate regions to bonding pads disposed on the semiconductor chips,
wherein the connection pads are electrically connected to the blind vias, and
wherein forming the conductive wires includes performing a test for confirming a current that flows between each conductive wire and the peripheral conductive pattern layer through the plurality of unit substrate regions.

2. The method of claim 1 , wherein the strip substrate of the unit substrate region comprises an insulation layer, an inner circuit pattern layer disposed in the insulation layer, and a first and a second outer circuit pattern layers disposed on a first and a second surfaces of the insulation layer, and wherein the inner circuit pattern layer electrically connects the blind via and the connection pattern layer.

3. The method of claim 1 , wherein the strip substrate of the unit substrate region includes multi-layered circuit pattern layers, and wherein the connection pattern layer is disposed on the same plane as the inner circuit pattern layer in contact with the blind via of the multi-layered circuit pattern layers.

4. The method of claim 1 , further comprising:
applying a voltage across circuit wires in the unit substrate regions through the blind via; and
performing an electric current test for the circuit wires before the step of disposing semiconductor chips on the plurality of unit substrate regions.

5. The method of claim 4 , wherein performing the electric current test for the circuit wires comprises applying a voltage to the circuit wires by bringing a probe of the tester into contact with the test pads electrically connected to the circuit wires and exposed on both surfaces of the strip substrate.

6. The method of claim 5 , wherein performing the electric current test for the circuit wires comprises performing an electric current test for one unit substrate region on the plurality of unit substrate regions, and performing an electric current test for the rest of the unit substrate regions of the plurality of unit substrate regions one by one.

7. The method of claim 4 , wherein the peripheral conductive pattern layer is electrically connected in common to the blind vias of the plurality of unit substrate regions.

8. The method of claim 1 , wherein the connection pattern layer is disposed on the same plane as the inner circuit pattern layer of the unit substrate region in contact with the blind via.

9. The method of claim 1 , wherein the peripheral conductive pattern layer comprises:
a first pattern portion disposed on the same plane as the connection pattern layer; and
a second pattern portion electrically connected to the first pattern portion by a conductive via and disposed on a surface of the insulation layer covering the first pattern portion.

10. The method of claim 1 , wherein forming the conductive wire comprises performing a first electric current test determining a bonding state between the end portion of the bonding wire and the connection pad, and
wherein performing the first electric current test comprises verifying a conduction state of the electric circuits formed inside the unit substrate region through the bonding wire and a bonding portion of the connection pad.

11. The method of claim 10 , wherein performing the first electric current test comprises verifying the conduction state of the electric circuits formed inside the unit substrate region through the bonding wire and the bonding portion of the connection pad.

12. The method of claim 10 , further comprising:
bonding the other end portion of the bonding wire on the bonding pad;
cutting the bonding wire; and
performing a second electric current test determining a cutting state of the bonding wire, and
wherein performing the second electric current test comprises verifying the conduction state of the electric circuits formed inside the unit substrate region through the bonding wire and the bonding portion of the connection pad.

13. The method of claim 12 , wherein performing the second electric current test comprises verifying the conduction state of the electric circuits formed inside the unit substrate region through the bonding wire and the bonding portion of the connection pad.

14. A method of testing a printed circuit board, the method comprising:
providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the peripheral conductive pattern layer to at least one blind via included in each of the plurality of unit substrate regions; and
performing a test for measuring a current flowing through each of the blind vias by applying a voltage across circuit wires electrically connected to the blind vias and disposed in the unit substrate regions,
wherein the peripheral conductive pattern layer is electrically connected to the blind vias of the plurality of unit substrate regions in common, and
wherein performing the test comprises performing an electric current test for measuring a current flowing through the blind via included in any one of the plurality unit substrate regions and sequentially performing the electric current test on remaining unit substrate regions.

15. The method of claim 14 , wherein performing the electric current test comprises applying a voltage to the circuit wires by bringing probes of a tester into contact with test pads that are electrically connected to the circuit wires and exposed on both edges of the strip substrate.

16. The method of claim 15 , wherein:
the connection pattern layer is disposed on the same plane as the inner circuit pattern layer of the unit substrate region;
the inner circuit pattern layer is in contact with the blind via; and
the connection pattern layer extends to the peripheral conductive pattern layer.

17. The method of claim 16 , wherein the peripheral conductive pattern layer comprises:
a first pattern portion disposed on the same plane as the connection pattern layer; and
a second pattern portion electrically connected to the first pattern portion by the conductive via and disposed on a surface of an insulation layer covering the first pattern portion.

Assignees

• Sk Hynix Inc
• Sk Hynix Ionc

Inventors

• Lee Ki Yong
• Kim Jong Hyun
• Choi Hyung Ju

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07531

  Techniques · CPC title

• H10W72/07521

  Aligning · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title