Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Semiconductor package and method of forming the same
US9502364B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502364-B2 |
| Application number | US-201414470999-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 28, 2014 |
| Priority date | Aug 28, 2014 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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- Title
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Abstract
Official abstract text for this publication.
According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a backside redistribution layer; at least one component, disposed over and connected to the backside redistribution layer; at least one chip adjacent to the at least one component; a molding compound disposed between the at least one chip and the at least one component; a via, disposed in the molding compound and connected to the backside redistribution layer; and a front redistribution layer, disposed over the chip and the via, wherein the chip and the at least one component are connected by using the backside redistribution layer, the via and the front redistribution layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a semiconductor package comprising a chip and a component, comprising: providing a temporary bonding layer over a carrier; forming an insulator layer over the temporary bonding layer; forming a backside redistribution layer over the insulator layer; providing a pre-solder over a portion of the backside redistribution layer; providing the chip and the component over the backside redistribution layer and contacting the component to…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9502364B2 cover?
- According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a backside redistribution layer; at least one component, disposed over and connected to the backside redistribution layer; at least one chip adjacent to the at least one component; a molding compound disposed between the at least one chip and the at least one component; a via, disposed…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W70/60. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).