Electronic package module and method for fabrication of the same
US-2024413067-A1 · Dec 12, 2024 · US
Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers
US9502363B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502363-B2 |
| Application number | US-201414223805-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 24, 2014 |
| Priority date | Mar 24, 2014 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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Abstract
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Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for producing a wafer level package, the method comprising: embedding a semiconductor die in a molded panel having a frontside surface at which the semiconductor die is exposed; forming inner redistribution layers over a semiconductor die by depositing a body of dielectric material over the frontside surface of the molded panel and producing metal routing features in the body of dielectric material electrically coupled to the semiconductor die, th…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9502363B2 cover?
- Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of die…
- Who is the assignee on this patent?
- Vincent Michael B, Duong Trung Q, Gong Zhiwei, and 7 more
- What technology area does this patent fall under?
- Primary CPC classification H10W74/014. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).