Field effect transistor with contact via structures that are laterally spaced by a sub-lithographic distance and method of making the same
US-2024063062-A1 · Feb 22, 2024 · US
Fabrication methods for multi-layer semiconductor structures
US9502301B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502301-B2 |
| Application number | US-201514730614-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 4, 2015 |
| Priority date | Dec 29, 2014 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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Abstract
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Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a substrate, the first layer including a first metal and the second layer including a second metal, where the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first layer, the second layer, and the substrate to react at least a portion of the first metal of the first layer to form a first reacted layer and at least a portion of the second metal of the second layer to form a second reacted layer, where at least one of the first reacted layer or the second reacted layer includes at least one of a first metal silicide of the first metal or a second metal silicide of the second metal.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: fabricating a semiconductor structure, the fabricating comprising: providing a first layer and a second layer above a substrate, the first layer comprising a first metal and the second layer comprising a second metal, wherein the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first layer and the second layer to react at least a portion of the first metal of th…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9502301B2 cover?
- Methods are provided for fabricating multi-layer semiconductor structures. The methods include, for example: providing a first layer and a second layer over a substrate, the first layer including a first metal and the second layer including a second metal, where the second layer is disposed over the first layer and the first metal and second metal are different metals; and annealing the first l…
- Who is the assignee on this patent?
- Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D84/0137. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).