Semiconductor magnetic memory device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9502291-B2
Application number	US-201514738814-A
Country	US
Kind code	B2
Filing date	Jun 12, 2015
Priority date	Jul 7, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A semiconductor memory device includes a first insulating layer covering a substrate, a first contact plug and a second contact plug each penetrating the first insulating layer, a first data storage element disposed on the first contact plug, and a second data storage element disposed on the second contact plug. The first contact plug includes a vertically extending portion and a horizontally extending portion arranged between the vertically extending portion and the first data storage element, and the second contact plug extends substantially vertically from a top surface of the substrate. The first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view. The first data storage element is disposed on the horizontally extending portion.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a first insulating layer covering a substrate;
a first contact plug and a second contact plug, each penetrating the first insulating layer;
a first data storage element disposed on the first contact plug and electrically connected to a portion of the substrate through the first contact plug; and
a second data storage element disposed on and overlapping the second contact plug and electrically connected to a portion of the substrate through the second contact plug,
wherein the first contact plug comprises:
a vertically extending portion; and
a horizontally extending portion arranged between the vertically extending portion and the first data storage element,
wherein the second contact plug vertically extends from a top surface of the substrate,
wherein the first data storage element is laterally spaced apart from the vertically extending portion,
wherein the first data storage element is disposed on the horizontally extending portion,
wherein a plurality of first contact plugs is provided and a plurality of second contact plugs is provided,
wherein the plurality of first contact plugs and the plurality of second contact plug are alternately and repeatedly arranged,
wherein each odd-numbered one of the contact plugs is one of the first contact plugs, and
wherein each even-numbered one of the contact plugs is one of the second contact plugs.

2. The semiconductor memory device of claim 1 , wherein the first insulating layer includes a recessed region that is disposed in an upper portion of the first insulating layer,
wherein a bottom surface of the recessed region is lower than a top surface of the first insulating layer, and
wherein the horizontally extending portion is provided in the recessed region.

3. The semiconductor memory device of claim 1 , wherein the horizontally extending portion is disposed on a top surface of the vertically extending portion, and
wherein the horizontally extending portion extends from the top surface of the vertically extending portion in a first direction or in a second direction that intersects the first direction.

4. The semiconductor memory device of claim 1 , wherein the horizontally extending portion is disposed on a top surface of the vertically extending portion, and
wherein the horizontally extending portion comprises:
a first portion extending from the top surface of the vertically extending portion in a first direction; and
a second portion extending from the first portion in a second direction that intersects the first direction.

5. The semiconductor memory device of claim 1 , further comprising:
a cell gate dielectric layer and a cell gate electrode sequentially disposed in a gate recess region intersecting a cell active portion defined in the substrate;
a first doped region and a second doped region disposed in the cell active portion at opposite sides of the gate recess region;
a second insulating layer disposed on the first insulating layer; and
a source line disposed in the first insulating layer and connected to the first doped region.

6. The semiconductor memory device of claim 5 , wherein the first contact plug and the second contact plug are arranged in a first direction,
wherein the source line is disposed between the first contact plug and the second contact plug and extends in a second direction that intersects the first direction, and
wherein the horizontally extending portion extends in the first direction or in a direction opposite to the first direction.

7. The semiconductor memory device of claim 5 , wherein the second insulating layer includes a recessed region that is disposed in an upper portion of the second insulating layer,
wherein a bottom surface of the recessed region of the second insulating layer is lower than a top surface of the second insulating layer and higher than a top surface of the source line, and
wherein the horizontally extending portion is provided in the recessed region of the second insulating layer.

8. The semiconductor memory device of claim 5 , wherein the plurality of first contact plugs and the plurality of second contact plugs are two-dimensionally arranged in a first row and a second row that are each parallel to a first direction,
wherein the second row is spaced apart from the first row in a second direction that intersects the first direction,
wherein each even-numbered contact plug of the second row is one of the first contact plugs, and
wherein each odd-numbered contact plug of the second row is one of the second contact plugs.

9. The semiconductor memory device of claim 8 , wherein the horizontally extending portions of the first row extend in the first direction, and
wherein the horizontally extending portions of the second row extend in a direction opposite to the first direction.

10. A semiconductor memory device, comprising:
a first insulating layer covering a substrate;
a plurality of first contact plugs penetrating the first insulating layer, each of the first contact plugs comprising a vertically extending portion extending substantially vertically from the substrate through the first insulating layer, and a horizontally extending portion extending substantially horizontally from a top surface of the vertically extending portion;
a plurality of second contact plugs penetrating the first insulating layer, each of the second contact plugs spaced apart from the first contact plug in a first direction, the plurality of first and second contact plugs being alternately and repeatedly arranged in a first row;
a first data storage element disposed on the horizontally extending portion of the first contact plug such that all or a portion of the first data storage element does not overlap the vertically extending portion of the first contact plug; and
a second data storage element disposed on and overlapping the second contact plug.

11. The semiconductor memory device of claim 10 , wherein the second contact plug extends substantially vertically from a top surface of the substrate.

12. The semiconductor memory device of claim 10 , wherein the horizontally extending portion extends from the top surface of the vertically extending portion in a first direction or in a second direction that intersects the first direction in a plan view.

13. The semiconductor memory device of claim 10 , further comprising a plurality of second and first contact plugs alternately and repeatedly arranged in a second row.

14. A semiconductor memory device, comprising:
an insulating layer covering a substrate;
a first contact plug and a second contact plug, the first and second contact plugs penetrating the insulating layer and sequentially arranged in a first row that is substantially parallel to a first direction,
a third contact plug and a fourth contact plug, the third and fourth contact plugs penetrating the insulating layer and sequentially arranged in a second row that is substantially parallel to the first direction;
a plurality of first data storage elements, a respective first data storage element being disposed on the first contact plug and on the fourth contact plug; and
a plurality of second data storage elements, a respective second data storage element being disposed on and overlapping the second contact plug and on and overlapping the third contact plug,
wherein each of the first and fourth contact plugs comprise:
a vertically extending portion extending substantially vertically from the substrate through the insulating layer; and
a horizontally extending portion arranged between the vertically extending portion and the firs

Assignees

• Lee Kilho
• Han Shinhee
• Samsung Electronics Co Ltd

Inventors

• Lee Kilho
• Han Shinhee

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/085

  involving intermediate temporary filling with material · CPC title