AVD hardmask for damascene patterning

Patent metadata

Field	Value
Publication number	US-9502281-B2
Application number	US-201113995133-A
Country	US
Kind code	B2
Filing date	Dec 29, 2011
Priority date	Dec 29, 2011
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having at least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.

First claim

The invention claimed is:

1. A method comprising:
forming a dielectric layer on a contact point of an integrated circuit structure;
forming a hardmask comprising a dielectric material on a surface of the dielectric layer;
forming an opening in the hardmask and a trench in the dielectric layer;
forming a sacrificial material in the trench and on the hardmask, wherein the sacrificed material is formed to a thickness greater than a depth of the trench to define a planar surface;
forming a mask on the sacrificial material, the mask having at least one opening for via formation;
etching the dielectric layer through the at least one opening in the mask to form at least one via in the dielectric layer to the contact point using the hardmask as a pattern; and
after forming the at least one via to the contact point, forming an interconnect in the via with the hardmask remaining on the dielectric layer.

2. The method of claim 1 , wherein the dielectric material of the hardmask comprises a dielectric constant greater than a dielectric constant of silicon dioxide.

3. The method of claim 2 , wherein the dielectric material of the hardmask is selected from the group consisting of silicon oxynitride, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride and lanthanum oxide.

4. The method of claim 2 , wherein a material of the dielectric layer comprises a dielectric constant less than a dielectric constant of silicon dioxide.

5. The method of claim 2 , wherein a material of the dielectric layer is porous.

6. The method of claim 1 , wherein the dielectric material of the hardmask has a density that is greater than a dielectric material of the dielectric layer.

7. The method of claim 1 , wherein forming a sacrificial material in the trench and on the hardmask comprises depositing a material to a thickness greater than a depth of the trench to define a planar surface.

8. A method comprising:
forming a dielectric layer on a contact point of an integrated circuit structure;
forming a first hardmask comprising a dielectric material on a surface of the dielectric layer;
forming a second hardmask comprising a conductive material on the first hardmask;
forming an opening in the first hardmask and the second hardmark and a trench in the dielectric layer;
forming a sacrificial material in the trench and on the hardmask;
forming a mask on the sacrificial material, the mask having at least one opening for via formation; and
etching the dielectric layer through the at least one opening in the mask to form at least one via in the dielectric layer to the contact point using the hardmask as a pattern.

9. The method of claim 8 , wherein after forming the at least one trench, removing the second hardmask.

10. A method comprising:
forming a dielectric layer comprising a first low K dielectric material on a contact point of an integrated circuit structure;
forming a hardmask comprising a second high K dielectric material on a surface of the dielectric layer;
patterning the hardmask for at least one trench;
forming the at least one trench in the dielectric layer; and
after forming the at least one trench,
forming a sacrificial material in the at least one trench and on the hardmask, wherein the sacrificial material is formed to a thickness greater than a depth of the trench to define a planar surface;
forming a mask on the sacrificial material, the mask having at least one opening for via formation;
etching the dielectric layer through the at least one opening in the mask to form at least one via in the dielectric layer to the contact point; and
forming an interconnect in the via to the contact point with the hardmask remaining on the dielectric layer.

11. The method of claim 10 , wherein the second high K dielectric material of the hardmask has a density that is greater than the first low K dielectric material of the dielectric layer.

12. The method of claim 10 , wherein the second high K dielectric material of the hardmask is selected from the group consisting of silicon oxynitride, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxynitride and lanthanum oxide.

13. The method of claim 10 , wherein forming a sacrificial material in the at least one trench and on the hardmask comprises depositing a material to a thickness greater than a depth of the trench to define a planar surface.

14. A method comprising:
forming a dielectric layer comprising a first low K dielectric material on a contact point of an integrated circuit structure;
forming a first hardmask comprising a second high K dielectric material on a surface of the dielectric layer;
forming a second hardmask comprising a conductive material on the first hardmask;
patterning the first hardmask and the second hardmask for at least one trench;
forming the at least one trench in the dielectric layer; and
after forming the at least one trench,
forming a sacrificial material in the at least one trench and on the hardmask;
forming a mask on the sacrificial material, the mask having at least one opening for via formation;
forming at least one via in the dielectric layer by etching through the at least one opening in the mask to the contact point; and
forming an interconnect in the via to the contact point with the hardmask remaining on the dielectric layer.

15. The method of claim 14 , wherein after forming the at least one trench, removing the second hardmask.

Assignees

• Brain Ruth A
• Fischer Kevin J
• Childs Michael A
• Intel Corp

Inventors

• Brain Ruth A
• Fischer Kevin J
• Childs Michael A

Classifications

• H10P50/28

  of insulating materials · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/081 Primary

  by forming openings in the dielectric parts · CPC title