Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof
US-9093457-B2 · Jul 28, 2015 · US
Devices and methods of packaging semiconductor devices
US9502272B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502272-B2 |
| Application number | US-201414584741-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 29, 2014 |
| Priority date | Dec 29, 2014 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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Abstract
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Devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a device includes a first semiconductor device and a second semiconductor device coupled to the first semiconductor device. An underfill material is disposed between the first semiconductor device and the second semiconductor device. The underfill material is also disposed on sidewalls of the first semiconductor device and the second semiconductor device. The underfill material has a first thickness on sidewalls of the first semiconductor device and a second thickness on sidewalls of the second semiconductor device. The second thickness is different than the first thickness.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of packaging a semiconductor device, the method comprising: providing a fan-out structure having a first plurality of electrodes; providing a packaged semiconductor device having a second plurality of electrodes; aligning the first and second plurality of electrodes; coupling the packaged semiconductor device to the fan-out structure by their respective electrodes using a plurality of connectors; partially singulating the coupled packaged se…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9502272B2 cover?
- Devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a device includes a first semiconductor device and a second semiconductor device coupled to the first semiconductor device. An underfill material is disposed between the first semiconductor device and the second semiconductor device. The underfill material is also disposed on sidewalls of the first semico…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).