Nanocrystalline diamond carbon film for 3D NAND hardmask application

Patent metadata

Field	Value
Publication number	US-9502262-B2
Application number	US-201514833858-A
Country	US
Kind code	B2
Filing date	Aug 24, 2015
Priority date	Sep 3, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer.

First claim

The invention claimed is:

1. A device comprising:
a substrate with a processing surface and a supporting surface;
a device layer formed on the processing surface, wherein the device layer is in contact with the processing surface; and
a nanocrystalline diamond layer formed on the device layer, wherein the nanocrystalline diamond layer is in contact with the device layer, and the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm; wherein each of the nanocrystalline diamond layer and device layer have a channel formed therein.

2. The device of claim 1 , wherein the nanocrystalline diamond layer further has surface roughness with a root mean square of height deviation of less than 6 nm.

3. The device of claim 1 , wherein the device layer comprises an electrically insulating material.

4. The device of claim 3 , wherein the device layer comprises silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

5. The device of claim 1 , wherein the device layer comprises a metal or a metal alloy.

6. The device of claim 5 , wherein the device layer comprises titanium, platinum, ruthenium, titanium nitride, hafnium nitride, tantalum nitride, zirconium nitride, or a metal silicide such as titanium silicide, nickel silicide, cobalt silicide, or a combination thereof.

7. The device of claim 1 , wherein the device layer comprises a semiconductor floating gate, conductive nanoparticles, or a discrete charge storage dielectric feature.

8. A method for processing a substrate, comprising:
depositing a device layer on a processing surface of a substrate, wherein the device layer is in contact with the processing surface, the substrate being positioned in a process chamber;
depositing a nanocrystalline diamond layer on the device layer, wherein the nanocrystalline diamond layer is in contact with the device layer, and the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm;
patterning and etching the nanocrystalline diamond layer;
etching the device layer to form a feature; and
ashing the nanocrystalline diamond layer from the surface of the device layer; wherein each of the nanocrystalline diamond layer and device layer have a channel formed therein.

9. The method of claim 8 , wherein the feature has an aspect ratio of greater than 50:1.

10. The method of claim 8 , wherein the substrate is maintained at a temperature of less than 600 degrees Celsius.

11. The method of claim 8 , further comprising forming a seed layer prior to depositing the nanocrystalline diamond layer.

12. A device comprising:
a substrate with a processing surface and a supporting surface;
a plurality of device layers formed on the processing surface, the plurality of device layers forming one or more components of a 3D NAND structure and having a plurality of channels formed through the plurality of device layers, each of the plurality of channels connecting to at least one of the one or more components; and
a nanocrystalline diamond layer formed on the plurality of device layers, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm; wherein each of the nanocrystalline diamond layer and device layer have a channel formed therein.

13. The device of claim 12 , wherein the nanocrystalline diamond layer further has surface roughness with a root mean square of height deviation of less than 6 nm.

14. The device of claim 12 , wherein at least one of the plurality of device layers comprises an electrically insulating material.

15. The device of claim 14 , wherein at least one of the plurality of device layers comprises silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

16. The device of claim 12 , wherein at least one of the plurality of device layers comprises a metal or a metal alloy.

17. The device of claim 16 , wherein at least one of the plurality of device layers comprises titanium, platinum, ruthenium, titanium nitride, hafnium nitride, tantalum nitride, zirconium nitride, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof.

18. The device of claim 12 , wherein at least one of the plurality of device layers comprises a semiconductor floating gate, conductive nanoparticles, or a discrete charge storage dielectric feature.

Assignees

• Applied Materials Inc

Inventors

• Chen Yongmei
• Ngai Christopher S
• Liu Jingjing
• Xue Jun
• Ying Chentsau
• Godet Ludovic

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P76/4083

  characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks · CPC title

• H10P50/285

  of materials not containing Si, e.g. PZT or Al2O3 · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title