Non-volatile memory device having asymmetrical control gates surrounding a floating gate and manufacturing method thereof

US9502257B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9502257-B2
Application numberUS-201414337418-A
CountryUS
Kind codeB2
Filing dateJul 22, 2014
Priority dateApr 23, 2014
Publication dateNov 22, 2016
Grant dateNov 22, 2016

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Abstract

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A non-volatile memory device and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a floating gate insulating layer and a floating gate disposed on a substrate, a dielectric layer formed perpendicular to the floating gate insulating layer and at two sides of the floating gate, and a first control gate at a first side of the dielectric layer distal from the floating gate and a second control gate at a second side of the dielectric layer distal from the floating gate, wherein the first control gate and the second control gate are connected to each other, and a second width of the second control gate is wider than a first width of the first control gate. A length of a control gate of a non-volatile memory device may be extended to effectively preventing the generation of leakage current when a control gate is off.

First claim

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What is claimed is: 1. A non-volatile memory device, the device comprising: a floating gate insulating layer disposed on a substrate; a floating gate insulated from the substrate by the floating gate insulating layer; a first dielectric region formed perpendicular to the floating gate insulating layer on a first sidewall of the floating gate; a second dielectric region formed perpendicular to the floating gate insulating layer on a second sidewall of the floating gate; a f…

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What does patent US9502257B2 cover?
A non-volatile memory device and a method of manufacturing the non-volatile memory device, where the non-volatile memory device includes a floating gate insulating layer and a floating gate disposed on a substrate, a dielectric layer formed perpendicular to the floating gate insulating layer and at two sides of the floating gate, and a first control gate at a first side of the dielectric layer …
Who is the assignee on this patent?
Magnachip Semiconductor Ltd
What technology area does this patent fall under?
Primary CPC classification H10D64/035. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).