Method and device for optimizing log likelihood ratio (LLR) used for nonvolatile memory device and for correcting errors in nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-9502137-B2
Application number	US-201414205482-A
Country	US
Kind code	B2
Filing date	Mar 12, 2014
Priority date	Mar 15, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

In a method of optimizing a log likelihood ratio (LLR) used to correct errors related to data stored in a nonvolatile memory device, variation of threshold voltage distribution for a plurality of memory cells included in the nonvolatile memory device is monitored, and the LLR for the memory cells is updated based on a monitoring result. Although the characteristics of the memory cells are deteriorated, the LLR is continuously maintained to the optimal value.

First claim

What is claimed is:

1. A method of optimizing a log likelihood ratio (LLR) used to correct errors related to data stored in a nonvolatile memory device, the method comprising:
monitoring a variation of a threshold voltage distribution for a plurality of memory cells included in the nonvolatile memory device; and
updating the LLR for the memory cells based on a result of the monitoring,
wherein the monitoring of the variation of the threshold voltage distribution comprises:
detecting a present threshold voltage distribution for the memory cells, and
estimating a variation direction and a variation degree of the variation of the threshold voltage distribution, including comparing a previously-stored initial threshold voltage distribution for the memory cells with the present threshold voltage distribution.

2. The method of claim 1 , wherein the initial threshold voltage distribution corresponds to a number of first memory cells, among the memory cells included in the nonvolatile memory device, having a threshold voltage which is less than a first voltage in an initial stage of an operation of the nonvolatile memory device and a number of second memory cells, among the memory cells included in the nonvolatile memory device, having a threshold voltage which is greater than a second voltage in the initial stage of the operation of the nonvolatile memory device among the memory cells, and
the present threshold voltage distribution corresponds to a number of third memory cells, among the memory cells included in the nonvolatile memory device, having a threshold voltage which is less than the first voltage in a present state of the nonvolatile memory device and a number of fourth memory cells, among the memory cells in the nonvolatile memory device, having a threshold voltage which is greater than the second voltage in the present state of the nonvolatile memory device.

3. The method of claim 2 , wherein each of the memory cells is a single level memory cell (SLC) to store one data bit therein, and
the first voltage is a voltage corresponding to an erased state, and the second voltage is a voltage corresponding to a programmed state.

4. The method of claim 2 , wherein each of the memory cells is a multi-level memory cell (MLC) to store a plurality of data bits therein; and
the first voltage is a voltage corresponding to an erased state, and the second voltage is a voltage corresponding to a programmed state having a highest level.

5. The method of claim 4 , wherein the MLC is a 2-bit memory cell to store 2-bit data, or a 3-bit memory cell to store 3-bit data.

6. The method of claim 1 , wherein the estimating is based on a difference between a number of first memory cells, among the plural memory cells of the nonvolatile memory device, having a threshold voltage between a first voltage and a second voltage in a present state of the nonvolatile memory device and a number of second memory cells, among the memory cells of the nonvolatile memory device, having a threshold voltage between the first voltage and a third voltage in the present state.

7. The method of claim 6 , wherein the first voltage is a voltage corresponding to a hard decision read-out operation, and the second and third voltages are voltages corresponding to a soft decision read-out operation.

8. The method of claim 1 , wherein the threshold voltage distribution is varied due to at least one of a disturbance between adjacent memory cells and an elapse of a data retention time.

9. The method of claim 8 , wherein the threshold voltage distribution is moved in a first direction due to the disturbance between the adjacent memory cells, and moved in a second direction different from the first direction due to the elapse of the data retention time.

10. A method of correcting errors related to data when reading out the data stored in a nonvolatile memory device, the method comprising:
optimizing a log-likelihood ratio (LLR) for a plurality of memory cells included in the nonvolatile memory device; and
performing error correction for the stored data based on the optimized LLR,
wherein the optimizing of the LLR comprises:
monitoring a variation of a threshold voltage distribution for the memory cells; and
updating the LLR for the memory cells based on a result of the monitoring,
wherein the monitoring of the variation of the threshold voltage distribution comprises:
detecting a present threshold voltage distribution for the memory cells, and
estimating a variation direction and a variation degree of the variation of the threshold voltage distribution, including comparing a previously-stored initial threshold voltage distribution for the memory cells with the present threshold voltage distribution.

11. The method of claim 10 , wherein the performing of the error correction for the stored data comprises:
performing error correction for the stored data by using a low density parity check (LDPC) code.

12. The method of claim 10 , wherein the optimizing of the LLR and the performing of the error correction are performed with a memory controller provided outside the nonvolatile memory device.

13. The method of claim 10 , wherein the nonvolatile memory device is a vertical-type memory device in which a plurality of word lines are vertically stacked.

14. The method of claim 10 , wherein the nonvolatile memory device comprises:
a memory cell array including the memory cells connected to a plurality of word lines and a plurality of bit lines;
a row decoder connected to the word lines; and
a page buffer connected to the bit lines.

15. An article of manufacture, comprising:
a log likelihood ratio (LLR) optimizer configured to optimize a log-likelihood ratio for a plurality of memory cells included in a nonvolatile memory device; and
an error correction code (ECC) decoder configured to perform error correction for the stored data based on the optimized LLR,
wherein the LLR optimizer is configured:
to monitor a variation of a threshold voltage distribution for the memory cells, wherein the monitoring of the variation of the threshold voltage distribution comprises:
detecting a present threshold voltage distribution for the memory cells, and
estimating a variation direction and a variation degree of the variation of the threshold voltage distribution, including comparing a previously-stored initial threshold voltage distribution for the memory cells with the present threshold voltage distribution, and

to update the LLR for the memory cells based on a result of the monitoring.

16. The article of manufacture of claim 15 , comprising a memory controller including the log likelihood ratio optimizer and the ECC decoder.

17. The article of manufacture of claim 16 , further comprising the nonvolatile memory device.

18. The article of manufacture of claim 15 , wherein the log likelihood ratio optimizer is configured to monitor the variation of the threshold voltage distribution by:
estimating the variation direction and the variation degree of the threshold voltage distribution based on a difference between a number of first memory cells, among the plural memory cells of the nonvolatile memory device, having a threshold voltage between a first voltage and a second voltage in a present state of the nonvolatile memory device, and a number of second memory cells, among the memory cells of the nonvolatile memory device, having a threshold voltage between the first voltage and a third voltage in the present state.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Sang-Yong
• Kim Kyung-Ryun
• Chun Jin-Young

Classifications

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• H03M13/3927

  Log-Likelihood Ratio [LLR] computation by combination of forward and backward metrics into LLRs · CPC title

• G11C29/026

  in sense amplifiers · CPC title