Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9502103-B1
Application number	US-201615068744-A
Country	US
Kind code	B1
Filing date	Mar 14, 2016
Priority date	Oct 6, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A semiconductor memory device according to an embodiment includes: a semiconductor substrate; and a memory cell array which is arranged above the semiconductor substrate in a first direction. The memory cell array includes: a semiconductor layer which extends in the first direction; a first conductive line which extends in a second direction crossing the first direction; a variable resistance film which is arranged at an intersection between the semiconductor layer and the first conductive line; a plurality of second conductive lines which are arranged in the second direction sandwiching the semiconductor layer and extend in the first direction; and a plurality of third conductive lines which are electrically connected to the second conductive lines. Two of the second conductive lines neighboring to each other in the second direction with the semiconductor layer interposed therebetween are electrically connected to different third conductive lines.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a semiconductor substrate; and
a memory cell array which is arranged above the semiconductor substrate in a first direction,
the memory cell array including:
a semiconductor layer which extends in the first direction;
a first conductive line which extends in a second direction crossing the first direction;
a variable resistance film which is arranged at an intersection between the semiconductor layer and the…

Assignees

• Toshiba Kk

Inventors

• Tanimoto Hiroyoshi
• Izumida Takashi

Classifications

• H01L45/146

  Electricity · mapped topic

• G11C13/0069

  Physics · mapped topic

• G11C13/0026

  Physics · mapped topic

• G11C13/0007 Primary

  Physics · mapped topic

• H01L23/528

  Electricity · mapped topic