Serial advanced technology attachment dual in-line memory module device
US-8942057-B1 · Jan 27, 2015 · US
Passive interface for an electronic memory device
US9502079B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9502079-B2 |
| Application number | US-201213883057-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 18, 2012 |
| Priority date | Feb 1, 2011 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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Abstract
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A passive interface for connecting an electronic memory device to an exterior circuit is provided. The passive interface includes a signal connection point, a power connection point and a ground connection point on an electronic memory device. A first passive component forms an electrical connection between the signal connection point and the power connection point. A second passive component forms an electrical connection between the power connection point and the ground connection point. And the power connection point receives a conditioned voltage signal through the electrical connection between the signal connection point and the power connection point. Such a passive interface can be used in a variety of devices, including headsets for intrinsically save applications.
First claim
Opening claim text (preview).
What is claimed is: 1. A passive interface for an electronic memory device, the passive interface comprising: a signal connection point, a power connection point and a ground connection point on an electronic memory device; a first passive component forming an electrical connection between the signal connection point and a second passive component; the second passive component forming an electrical connection between the ground connection point and the first passive component;…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Cross-Sectional Technologies · mapped topic
- G11C5/06Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US9502079B2 cover?
- A passive interface for connecting an electronic memory device to an exterior circuit is provided. The passive interface includes a signal connection point, a power connection point and a ground connection point on an electronic memory device. A first passive component forms an electrical connection between the signal connection point and the power connection point. A second passive component f…
- Who is the assignee on this patent?
- Henry Paul D, 3M Innovative Properties Co
- What technology area does this patent fall under?
- Primary CPC classification G11C5/06. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).