Identifying the cause of timing failure of an IC design using sequential timing

Patent metadata

Field	Value
Publication number	US-9501606-B2
Application number	US-201414582984-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Dec 30, 2013
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of nodes representing IC components. The method identifies several paths in the graph that each starts from a timed source node and ends to a timed target node. Each path includes several clocked elements and several computational elements. The method optimizes the timing performance of the IC design by skewing clock signals to one or more clocked elements to satisfy a set of timing constraints. For each identified path, the method determines the ratio of signal travel time from the source node to the destination node to a maximum time allocated for the data signal to travel from the source node to the target node. When the IC design fails timing constraints, the path that has a maximum determined ratio as a cause for timing failure.

First claim

What is claimed is:

1. A method of optimizing timing performance of an IC design, the IC design expressed as a graph comprising a plurality of nodes representing IC components, the method comprising:
identifying a plurality of paths in the graph, each path starting from a timed source node and ending to a timed target node, each path comprising a plurality of clocked elements and a plurality of computational elements;
optimizing the timing performance of the IC design by skewing…

Assignees

• Altera Corp

Inventors

• Teig Steven
• Caldwell Andrew

Classifications

• G06F2119/12

  Physics · mapped topic

• G06F30/3312

  Physics · mapped topic

• G06F30/20

  Physics · mapped topic

• G06F30/398 Primary

  Physics · mapped topic

• G06F30/327 Primary

  Physics · mapped topic