System and method for computer memory with linked paths

Patent metadata

Field	Value
Publication number	US-9501432-B2
Application number	US-201414246643-A
Country	US
Kind code	B2
Filing date	Apr 7, 2014
Priority date	Mar 20, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer.

First claim

What is claimed is:

1. A method for memory mirroring, the method comprising:
disabling a first connection between a first memory buffer and a first memory controller, the first memory buffer having a first high speed memory channel and a second high speed memory channel, the first connection connected to the first memory buffer through the first high speed memory channel;
enabling a second connection between a second memory buffer and the first memory buffer, the second memory b…

Assignees

• IBM

Inventors

• Cordero Edgar R
• Paulraj Girisankar
• Chinnakkonda Vidyapoornachary Diyanesh B

Classifications

• G06F2212/7203

  Physics · mapped topic

• G06F12/0246

  Physics · mapped topic

• G06F13/1673 Primary

  Physics · mapped topic

• G06F3/065

  Physics · mapped topic

• G06F2212/7208

  Physics · mapped topic