Translation lookaside buffer management

Patent metadata

Field	Value
Publication number	US-9501425-B2
Application number	US-201414541498-A
Country	US
Kind code	B2
Filing date	Nov 14, 2014
Priority date	Nov 14, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

Each of multiple translation lookaside buffers (TLBs) is associated with a corresponding processing element. A first TLB invalidation (TLBI) instruction is issued at a first processing element, and sent to a second processing element. An element-specific synchronization instruction is issued at the first processing element. A synchronization command is broadcast, and received at the second processing element. The element-specific synchronization instruction prevents issuance of additional TLBI instructions at the first processing element until an acknowledgement in response to the synchronization command is received at the first processing element. After completion of any TLBI instructions issued at the second processing element before the synchronization command was received, the acknowledgement is sent from the second processing element to the first processing element, indicating that any TLBI instructions issued at the second processing element before the synchronization command was received at the second processing element are complete.

First claim

What is claimed is:

1. A method for managing a plurality of translation lookaside buffers, each translation lookaside buffer being associated with a corresponding processing element of a plurality of processing elements, the method comprising:
issuing a first translation lookaside buffer invalidation instruction at a first processing element of the plurality of processing elements, and sending the first translation lookaside buffer invalidation instruction to a second processing element of the plurality of processing elements;
receiving translation lookaside buffer invalidation instructions, including the first translation lookaside buffer invalidation instruction, at the second processing element;
issuing an element-specific synchronization instruction at the first processing element, and broadcasting a synchronization command to multiple processing elements, the element-specific synchronization instruction being issued without being broadcast to multiple processing elements and the element-specific synchronization instruction preventing issuance of additional translation lookaside buffer invalidation instructions at the first processing element until an acknowledgement in response to the synchronization command is received at the first processing element;
receiving the synchronization command at the second processing element; and
after completion of any translation lookaside buffer invalidation instructions, including the first translation lookaside buffer invalidation instruction, issued at the second processing element before the synchronization command was received at the second processing element, sending the acknowledgement from the second processing element to the first processing element, the acknowledgement indicating that any translation lookaside buffer invalidation instructions, including the first translation lookaside buffer invalidation instruction, issued at the second processing element before the synchronization command was received at the second processing element are complete.

2. The method of claim 1 wherein the acknowledgement indicates that a plurality of translation lookaside buffer invalidation instructions issued at the second processing element before the synchronization command was received at the second processing element are complete.

3. The method of claim 2 wherein two or more translation lookaside buffer invalidation instructions of the plurality of translation lookaside buffer invalidation instructions were received at the second processing element from other processing elements of the plurality of processing elements.

4. The method of claim 1 wherein the acknowledgement further indicates that any write operations present in a write buffer of the second processing element prior to the synchronization command being received at the second processing element are complete.

5. The method of claim 1 wherein sending the first translation lookaside buffer invalidation instruction to the second processing element includes sending the first translation lookaside buffer invalidation instruction to a broadcast element and subsequently sending the first translation lookaside buffer invalidation instruction from the broadcast element to the second processing element.

6. The method of claim 5 wherein the broadcast element maintains a count of translation lookaside buffer invalidation instructions received since the last synchronization command was received.

7. The method of claim 6 further comprising receiving a second synchronization command at the broadcast element and determining whether or not to send the second synchronization command to one or more processing elements of the plurality of processing elements based on the count of translation lookaside buffer invalidation instructions received since the last synchronization command was received.

8. The method of claim 7 further comprising sending the second synchronization command to the one or more processing elements of the plurality of processing elements if the count of translation lookaside buffer invalidation instructions received since the last synchronization command was received is greater than zero and suppressing the second synchronization command if the count of translation lookaside buffer invalidation instructions received since the last synchronization command was received is equal to zero.

9. The method of claim 6 wherein the broadcast element increments the count of translation lookaside buffer invalidation instructions received since the last synchronization command was received upon receiving the first translation lookaside buffer invalidation instruction.

10. The method of claim 5 wherein broadcasting the synchronization command includes sending the synchronization command to the broadcast element and subsequently sending the synchronization command from the broadcast element to the second processing element.

11. The method of claim 10 wherein the broadcast element resets the count of translation lookaside buffer invalidation instructions received since the last synchronization command was received to zero upon receiving the synchronization command.

12. The method of claim 5 further comprising sending the synchronization instruction from the broadcast element to a second broadcast element, wherein the second broadcast element subsequently sends the synchronization instruction to one or more processor elements of a second plurality of processor elements.

13. The method of claim 1 wherein broadcasting the synchronization command includes broadcasting the synchronization command through a broadcast element that maintains a count of translation lookaside buffer invalidation instructions received since the last synchronization command was received.

14. An apparatus comprising:
a plurality of processing elements, each processing element being associated with a corresponding translation lookaside buffer;
wherein a first processing element of the plurality of processing elements is configured to issue a first translation lookaside buffer invalidation instruction, and send the first translation lookaside buffer invalidation instruction to a second processing element of the plurality of processing elements;
wherein the second processing element is configured to receive translation lookaside buffer invalidation instructions, including the first translation lookaside buffer invalidation instruction;
wherein the first processing element is configured to issue an element-specific synchronization instruction, and broadcasting a synchronization command to multiple processing elements, the element-specific synchronization instruction being issued without being broadcast to multiple processing elements and the element-specific synchronization instruction preventing issuance of additional translation lookaside buffer invalidation instructions at the first processing element until an acknowledgement in response to the synchronization command is received at the first processing element;
wherein the second processing element is configured to receive the synchronization command; and
wherein, after completion of any translation lookaside buffer invalidation instructions, including the first translation lookaside buffer invalidation instruction, issued at the second processing element before the synchronization command was received at the second processing element, the second processing element is configured to send the acknowledgement to the first processing element, the acknowledgement indicating that any translation lookaside buffer invalidation instructions, including the first translation lookaside buffer invalidation instruction, issued at the second processin

Assignees

• Cavium Inc

Inventors

• Mukherjee Shubhendu S
• Asher David
• Bertone Mike
• Dobbie Bradley
• Hummel Thomas

Classifications

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F2212/683

  Invalidation · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title