Parallel Processing Of Data
US-2024338235-A1 · Oct 10, 2024 · US
Scheduling threads according to real time bit in predetermined time period or in variable time period of requested time ratio
US9501320B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9501320-B2 |
| Application number | US-201314092498-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 27, 2013 |
| Priority date | Sep 30, 2008 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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Abstract
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A multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, and a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread. The thread scheduler specifies execution of at least one hardware thread pre-selected among the plurality of hardware threads in a predetermined first execution period, and specifies execution of a variably selected hardware thread in a second execution period other than the first execution period. A time ratio between the predetermined first execution period and the second execution period is set according to processing requests.
First claim
Opening claim text (preview).
What is claimed is: 1. A multi-thread processor comprising: a plurality of hardware threads each of which generates an independent instruction flow; a thread scheduler that outputs a thread selection signal in accordance with a schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle of the thread scheduler among the plurality of hardware threads; and a first selector that selects one of the plurality of hardware threads acco…
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Classifications
- G06F9/3851Primary
Physics · mapped topic
- G06F9/4881Primary
Physics · mapped topic
Physics · mapped topic
Cross-Sectional Technologies · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9501320B2 cover?
- A multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, and a first selector that selects one of the…
- Who is the assignee on this patent?
- Renesas Electronics Corp
- What technology area does this patent fall under?
- Primary CPC classification G06F9/3851. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).