Instructions and logic to vectorize conditional loops

US9501276B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9501276-B2
Application numberUS-201213731809-A
CountryUS
Kind codeB2
Filing dateDec 31, 2012
Priority dateDec 31, 2012
Publication dateNov 22, 2016
Grant dateNov 22, 2016

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Abstract

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Instructions and logic provide vectorization of conditional loops. A vector expand instruction has a parameter to specify a source vector, a parameter to specify a conditions mask register, and a destination parameter to specify a destination vector to hold n consecutive vector elements, each of the plurality of n consecutive vector elements having a same variable partition size of m bytes. In response to the processor instruction, data is copied from consecutive vector elements in the source vector, and expanded into unmasked vector elements of the specified destination vector, without copying data into masked vector elements of the destination vector, wherein n varies responsive to the processor instruction executed. The source vector may be a register and the destination vector may be in memory. Some embodiments store counts of the condition decisions. Alternative embodiments may store other data, for example such as target addresses, or table offsets, or indicators of processing directives, etc.

First claim

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What is claimed is: 1. A processor comprising: a source vector register; a destination vector register; a decode stage to decode a processor instruction specifying a vector expand operation and a data partition size; and one or more execution units, responsive to the decoded processor instruction, to: read values from each of a first plurality of n data fields of the source vector register, wherein each of the first plurality of n data fields is to store a vector element ha…

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What does patent US9501276B2 cover?
Instructions and logic provide vectorization of conditional loops. A vector expand instruction has a parameter to specify a source vector, a parameter to specify a conditions mask register, and a destination parameter to specify a destination vector to hold n consecutive vector elements, each of the plurality of n consecutive vector elements having a same variable partition size of m bytes. In …
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F9/30018. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).