Accelerating eight-way parallel keccak execution
US-2024211268-A1 · Jun 27, 2024 · US
US9501276B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9501276-B2 |
| Application number | US-201213731809-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 31, 2012 |
| Priority date | Dec 31, 2012 |
| Publication date | Nov 22, 2016 |
| Grant date | Nov 22, 2016 |
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Instructions and logic provide vectorization of conditional loops. A vector expand instruction has a parameter to specify a source vector, a parameter to specify a conditions mask register, and a destination parameter to specify a destination vector to hold n consecutive vector elements, each of the plurality of n consecutive vector elements having a same variable partition size of m bytes. In response to the processor instruction, data is copied from consecutive vector elements in the source vector, and expanded into unmasked vector elements of the specified destination vector, without copying data into masked vector elements of the destination vector, wherein n varies responsive to the processor instruction executed. The source vector may be a register and the destination vector may be in memory. Some embodiments store counts of the condition decisions. Alternative embodiments may store other data, for example such as target addresses, or table offsets, or indicators of processing directives, etc.
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What is claimed is: 1. A processor comprising: a source vector register; a destination vector register; a decode stage to decode a processor instruction specifying a vector expand operation and a data partition size; and one or more execution units, responsive to the decoded processor instruction, to: read values from each of a first plurality of n data fields of the source vector register, wherein each of the first plurality of n data fields is to store a vector element ha…
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