Surface inspection apparatus for semiconductor chips

US9500599B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9500599-B2
Application numberUS-201514603809-A
CountryUS
Kind codeB2
Filing dateJan 23, 2015
Priority dateJan 23, 2014
Publication dateNov 22, 2016
Grant dateNov 22, 2016

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A surface inspection apparatus and method of inspecting chip surfaces includes a laser generator that generates a periodic CW laser and is transformed into an inspection laser beam having a beam size smaller than a surface size of the chip. Thus, the inspection laser beam is irradiated onto a plurality of the semiconductor chips such that the semiconductor chips are partially and simultaneously heated. Thermal waves are detected in response to the inspection laser beam and thermal images are generated corresponding to the thermal waves. A surface image is generated by a lock-in thermography technique and hold exponent analysis of the thermal image, thereby generating surface image in which a surface defect is included. Time and accuracy of the surface inspection process is improved.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus for inspecting surfaces of semiconductor chips, comprising: a laser generator generating a periodic continuous wave (CW) laser; a laser controller transforming the periodic CW laser into an inspection laser beam of which a beam size is smaller than a surface size of the semiconductor chip and irradiating the inspection laser beam onto a plurality of the semiconductor chips such that the semiconductor chips are partially and simultaneously heat…

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What does patent US9500599B2 cover?
A surface inspection apparatus and method of inspecting chip surfaces includes a laser generator that generates a periodic CW laser and is transformed into an inspection laser beam having a beam size smaller than a surface size of the chip. Thus, the inspection laser beam is irradiated onto a plurality of the semiconductor chips such that the semiconductor chips are partially and simultaneously…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G01N21/9501. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).