Analog to digital converter with internal timer

Patent metadata

Field	Value
Publication number	US-9496887-B1
Application number	US-201514710105-A
Country	US
Kind code	B1
Filing date	May 12, 2015
Priority date	May 12, 2015
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time.

First claim

What is claimed is:

1. A method for operating an analog-to-digital converter, comprising:
receiving a sampling time;
receiving a conversion time;
determining a power up time from at least one sleep mode; and
entering the analog-to-digital converter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time.

2. The method according to claim 1 , wherein the at least one sleep mode comprises a plurality of sleep modes and the determining a power up time comprises determining power up times associated with each of the plurality of sleep modes.

3. The method according to claim 2 , wherein the entering the analog-to-digital converter into the at least one sleep mode comprises entering the analog-to-digital converter into a lowest power of the plurality of sleep modes whose sum of respective power up time and conversion time is less than the sampling time.

4. The method according to claim 3 , wherein determining a power up time comprises an estimated power up time.

5. The method according to claim 1 , wherein the sampling time, the conversion time, and the power up time are converted to a number of clock periods.

6. The method according to claim 3 , further comprising transitioning from a first low power state to a second low power state, the transitioning comprising comparing a power up time of the second low power state with an elapsed power up time count of the first low power state and resetting a count to the power up time of the second low power state if the power up time of the second low power state is greater than a time remaining for the first power up time.

7. The method according to claim 6 , further comprising continuing the count if the elapsed power up time count is greater than power up time of the second low power state.

8. A non-transitory computer-readable medium containing instructions which when implemented by a computer perform a method for operating an analog-to-digital converter, comprising:
receiving a sampling time;
receiving a conversion time;
determining a power up time from at least one sleep mode; and
entering the analog-to-digital converter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time.

9. The non-transitory computer-readable medium according to claim 8 , wherein the at least one sleep mode comprises a plurality of sleep modes and the determining a power up time comprises determining power up times associated with each of the plurality of sleep modes.

10. The non-transitory computer-readable medium according to claim 9 , wherein the entering the analog-to-digital converter into the at least one sleep mode comprises entering the analog-to-digital converter into a lowest power of the plurality of sleep modes whose sum of power up time and conversion time is less than the sampling time.

11. The non-transitory computer-readable medium according to claim 10 , wherein determining a power up time comprises an estimated power up time.

12. The non-transitory computer-readable medium according to claim 9 , wherein the sampling time, the conversion time, and the power up time are converted to a number of clock periods.

13. The non-transitory computer-readable medium according to claim 12 , further comprising transitioning from a first low power state to a second low power state, the transitioning comprising comparing a power up time of the second low power state with an elapsed power up time count of the first low power state and resetting a count to the power up time of the second low power state if the power up time of the second low power state is greater than a time remaining for the first power up time.

14. The non-transitory computer-readable medium according to claim 13 , further comprising continuing the count if the elapsed power up time count is greater than power up time of the second low power state.

15. An analog-to-digital converter, comprising:
circuitry for receiving an analog input and converting the input to a digital signal; and
non-transitory control circuitry configured for:
receiving a sampling time;
receiving a conversion time;
determining a power up time from at least one sleep mode; and
causing the analog-to-digital converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time.

16. The analog-to-digital converter according to claim 15 , wherein the at least one sleep mode comprises a plurality of sleep modes and the determining a power up time comprises determining power up times associated with each of the plurality of sleep modes.

17. The analog-to-digital converter according to claim 16 , wherein the entering the analog-to-digital converter into the at least one sleep mode comprises entering the analog-to-digital converter into a lowest power of the plurality of sleep modes whose sum of power up time and conversion time is less than the sampling time.

18. The analog-to-digital converter according to claim 17 , wherein determining a power up time comprises an estimated power up time.

19. The analog-to-digital converter according to claim 15 , wherein the sampling time, the conversion time, and the power up time are converted to a number of clock periods.

20. The analog-to-digital converter according to claim 17 , further comprising transitioning from a first low power state to a second low power state, the transitioning comprising comparing a power up time of the second low power state with an elapsed power up time count of the first low power state and resetting a count to the power up time of the second low power state if the power up time of the second low power state is greater than a time remaining for the first power up time.

21. The analog-to-digital converter according to claim 20 , further comprising continuing the count if the elapsed power up time count is greater than power up time of the second low power state.

Assignees

• Microchip Tech Inc

Inventors

• Quiquempoix Vincent
• Barreto Alexandre

Classifications

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• G06F1/325

  Power saving in peripheral device · CPC title

• H03M1/34 Primary

  Analogue value compared with reference values (H03M1/48 takes precedence) · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title