Via resistance analysis systems and methods

Patent metadata

Field	Value
Publication number	US-9496853-B2
Application number	US-201213556129-A
Country	US
Kind code	B2
Filing date	Jul 23, 2012
Priority date	Jul 22, 2011
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer, which can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map and can include correlation of the via resistance into a wafer.

First claim

What is claimed is:

1. A ring oscillator comprising:
at least one inversion stage operable to cause a signal transition; wherein said inverting stage is coupled to another component through a via layer in which a resistance due to characteristics of the via layer coupling has a relatively significant impact on a transition of a signal through a ring path, wherein the coupling through the via layer is configured to facilitate misalignment analysis, including distinguishing whether the impact is due to misalignment or not; and
an output component for outputting an indication of the impact the via resistance has on the signal transition of the signal through the ring oscillator.

2. A ring oscillator of claim 1 in which the coupling through the via layer includes a first horizontal metal layer component at one level and a second horizontal metal layer component at another level and a vertical component coupling the first horizontal metal layer component at one level and a second horizontal metal layer at another level.

3. A ring oscillator of claim 2 wherein the first horizontal metal layer component, the second horizontal metal layer component and the vertical component are configured to form a reduced coupling enclosure area for increased sensitivity to misalignment.

4. A ring oscillator of claim 2 wherein the first horizontal metal layer component, the second horizontal metal layer component and the vertical component are configured to form an enlarged coupling enclosure area for reduced sensitivity to misalignment.

5. A ring oscillator of claim 2 wherein the vertical component is wide compared to the first horizontal component and second horizontal component.

6. A ring oscillator of claim 2 wherein the vertical component is narrow compared to the first horizontal component and second horizontal component.

7. A ring oscillator of claim 1 wherein the via resistance is significantly higher than the channel resistance of a driving transistor.

8. A method comprising:
performing a dominant characteristic ring oscillation process, wherein a dominant characteristic facilitates via misalignment-analysis, including distinguishing whether the impact is due to misalignment or not; and
analyzing results of the dominant characteristic ring oscillation process, including analyzing misalignment.

9. The method of claim 8 wherein the analysis includes determining a delay associated with a via resistance characteristic of dominant via resistance ring oscillation process.

10. The method of claim 8 wherein the analysis includes correlating a delay associated with at least one of a dominant via resistance characteristic oscillation rings to a process variation.

11. The method of claim 8 wherein the analysis includes deconvolving transistor speed.

12. The method of claim 8 wherein the analysis includes deconvolving metal resistance.

13. The method of claim 8 wherein the analyzing comprises:
examining large enclosure ring oscillator where via resistance plays a relatively very small role in delay;
examining small enclosure ring oscillator where via resistance plays a relatively very large role in delay; and
determining the via resistance difference due to via discontinuity.

14. A ring oscillator comprising:
at least one inversion stage operable to cause a signal transition;
a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator, wherein the target component facilitates via misalignment analysis, including distinguishing whether the impact is due to misalignment or not; and
an output component for outputting an indication of the impact the target component has on the signal transition.

15. A ring oscillator of claim 14 wherein the target component includes a plurality of vias from one metal layer to another metal layer.

16. A ring oscillator of claim 15 wherein the plurality of vias from one metal layer to another metal layer are configured in a cell.

17. A ring oscillator of claim 14 wherein vias corresponds to a via layer.

18. The ring oscillator of claim 14 wherein the output is coupled to an analysis component.

19. A ring oscillator of claim 14 wherein an analysis component can include correlation of a via resistance into a wafer variations and generate a wafer map.

20. The ring oscillator of claim 14 further comprising a control component coupled to the ring path to control a state of the signal.

Assignees

• Poppe Wojciech Jakub
• Gupta Puneet
• Elkin Ilyas
• Nvidia Corp

Inventors

• Poppe Wojciech Jakub
• Gupta Puneet
• Elkin Ilyas

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• G01R31/2831

  Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00) · CPC title

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• H03K3/0315 Primary

  Ring oscillators · CPC title

• H01L2924/00

  Electricity · mapped topic