Performance of off-chip connection for power amplifier

Patent metadata

Field	Value
Publication number	US-9496832-B2
Application number	US-201514598927-A
Country	US
Kind code	B2
Filing date	Jan 16, 2015
Priority date	Jun 11, 2010
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

There is provided an amplifier arrangement comprising: a main amplifier connected to receive an input signal and generate an amplified version of the input signal; an additional amplifier, having a smaller geometry than the main amplifier, connected to receive the input signal and generate an amplified version thereof; and wherein the outputs of the main amplifier and the additional amplifier are combined to provide an amplified output.

First claim

What is claimed is:

1. An amplifier arrangement provided on an integrated circuit, comprising:
a high pass filter configured to receive a first input signal and provide a high pass filtered version of the first input signal;
a phase splitter configured to generate a second input signal and a third input signal, based on the first input signal, such that the second and the third input signals have different phases;
a main amplifier configured to amplify the second and the third input signals having different phases to generate an output of the main amplifier, wherein the main amplifier comprises a first push-pull amplifier and a second push-pull amplifier, and wherein at least one output of the first push-pull amplifier and at least one output of the second push-pull amplifier are combined to generate the output of the main amplifier; and
an additional amplifier configured to amplify the high pass filtered version of the first input signal to generate an output of the additional amplifier, wherein the outputs of the main amplifier and the additional amplifier are combined to provide an amplified output of the amplifier arrangement.

2. The amplifier arrangement of claim 1 , wherein the outputs of the main amplifier and the additional amplifier are connected to a respective pair of bond wires.

3. The amplifier arrangement of claim 1 , wherein during operation in a crossover region of the main amplifier, a bandwidth of the additional amplifier is greater than a bandwidth of the main amplifier.

4. The amplifier arrangement of claim 3 , wherein during operation in the crossover region of the main amplifier, the bandwidth of the main amplifier is reduced compared to the bandwidth of the main amplifier during operation outside the crossover region.

5. The amplifier of claim 1 , wherein during operation when a bandwidth of the main amplifier is reduced, a bandwidth of the additional amplifier is greater than the bandwidth of the main amplifier.

6. The amplifier of claim 1 , wherein during operation when a bandwidth of the main amplifier is reduced, a bandwidth of the additional amplifier is maintained at a level corresponding to the bandwidth of the main amplifier before the bandwidth of the main amplifier was reduced.

7. The amplifier of claim 1 , wherein a bias current of the main amplifier is set in dependence on a level of bias current required to provide a required bandwidth outside a crossover region of operation.

8. The amplifier of claim 1 , wherein a bias current of the main amplifier is set in dependence on a level of bias current to achieve a desired bandwidth of operation with an output transistor of a push or pull side of the first push-pull amplifier fully turned on.

9. The amplifier arrangement of claim 1 , wherein the additional amplifier increases an overall bandwidth of the amplifier arrangement, during a period in which a bandwidth of the main amplifier is reduced, such that a phase shift between the first input signal and the amplified output of the amplifier arrangement is reduced relative to a phase shift between the first input signal and the output of the main amplifier.

10. The amplifier arrangement of claim 1 , wherein the additional amplifier increases an overall bandwidth of the amplifier arrangement, during a period in which a bandwidth of the main amplifier is reduced, such that the bandwidth of the main amplifier is reduced relative to the bandwidth of the main amplifier without the additional amplifier, wherein a bias current of the main amplifier is reduced relative to the bias current of the main amplifier without the additional amplifier.

11. The amplifier arrangement of claim 1 , wherein the main amplifier is a power amplifier.

12. The amplifier arrangement of claim 1 , wherein the main amplifier comprises a current mirror arrangement for driving an output transistor.

13. A method of amplifying a first input signal, comprising:
high pass filtering a first input signal to provide a high pass filtered version of the first input signal;
phase splitting the first input signal to generate a second input signal and a third input signal such that the second and the third input signals have different phases;
amplifying, on an integrated circuit, the second and the third input signals having different phases via a main amplifier to generate an output of the main amplifier, wherein the main amplifier comprises a first push-pull amplifier and a second push-pull amplifier and wherein at least one output of the first push-pull amplifier and at least one output of the second push-pull amplifier are combined to generate the output of the main amplifier;
amplifying, on the integrated circuit, the high pass filtered version of the first input signal in via an additional amplifier to generate an output of the additional amplifier;
combining the outputs of the main amplifier and the additional amplifier off-chip to provide an amplified output.

14. The method of claim 13 , further comprising providing a bias current for the main amplifier determined in dependence on a predetermined bandwidth of operation of the main amplifier.

15. The method of claim 14 , wherein in any region of operation of the main amplifier where the bandwidth of operation of the main amplifier is reduced, the bandwidth of operation of the additional amplifier provides for full bandwidth operation.

16. The method of claim 14 , wherein a bias current for the additional amplifier, which is less than the bias current for the main amplifier, is determined in dependence on a predetermined bandwidth of operation for the additional amplifier which corresponds to the bandwidth of operation of the main amplifier.

17. The method of claim 14 , wherein the bias current of the main amplifier is reduced compared to the bias current required for the main amplifier if the additional amplifier was not provided.

18. The method of claim 14 , wherein the bias current is determined in dependence on a level of bias current required to achieve a predetermined bandwidth with either output transistor of the first push-pull amplifier turned on.

19. An amplifier arrangement provided on an integrated circuit, comprising:
a main push-pull amplifier connected to receive an input signal and generate an amplified version of the input signal;
a high pass filter connected to receive the input signal and provide a high pass filtered version of the input signal; and
an additional amplifier connected to receive the high pass filtered version of the input signal and generate an amplified version thereof, wherein an output of the main push-pull amplifier and an output of the additional amplifier are combined to provide an amplified output and wherein the additional amplifier is configured to increase the overall bandwidth of the amplifier arrangement, during a period in which the bandwidth of the main amplifier is reduced, such that a phase shift between the input signal and the amplified output is reduced relative to the phase shift between the input signal and the output of the main amplifier.

Assignees

• Snaptrack Inc

Inventors

• Wilson Martin Paul

Classifications

• H03F2203/30006

  the push and the pull stages of the SEPP amplifier are both current mirrors · CPC title

• H03F2203/21106

  An input signal being distributed in parallel over the inputs of a plurality of power amplifiers · CPC title

• H03F3/195 Primary

  in integrated circuits · CPC title

• H03F2200/36

  the amplifier comprising means for increasing the bandwidth · CPC title

• H03F2203/21112

  A filter circuit being added at the input of a power amplifier stage · CPC title