Metal gate with silicon sidewall spacers

US9496402B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9496402-B2
Application numberUS-201514801319-A
CountryUS
Kind codeB2
Filing dateJul 16, 2015
Priority dateOct 17, 2014
Publication dateNov 15, 2016
Grant dateNov 15, 2016

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  1. Title

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  2. Abstract

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method includes forming an opening in a dielectric to reveal a protruding semiconductor fin, forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin, and forming a conductive diffusion barrier layer over the gate dielectric. The conductive diffusion barrier layer extends into the opening. The method further includes forming a silicon layer over the conductive diffusion barrier layer and extending into the opening, and performing a dry etch on the silicon layer to remove horizontal portions and vertical portions of the silicon layer. After the dry etch, a conductive layer is formed over the conductive diffusion barrier layer and extending into the opening.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: forming an opening in a dielectric to reveal a protruding semiconductor fin; forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin; forming a conductive diffusion barrier layer over the gate dielectric, wherein the conductive diffusion barrier layer extends into the opening; forming a silicon layer over the conductive diffusion barrier layer and extending into the opening; performing a dry e…

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What does patent US9496402B2 cover?
A method includes forming an opening in a dielectric to reveal a protruding semiconductor fin, forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin, and forming a conductive diffusion barrier layer over the gate dielectric. The conductive diffusion barrier layer extends into the opening. The method further includes forming a silicon layer over the conduct…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D64/01. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 15 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).