III-V device structure with multiple threshold voltage

Patent metadata

Field	Value
Publication number	US-9496401-B1
Application number	US-201514755520-A
Country	US
Kind code	B1
Filing date	Jun 30, 2015
Priority date	Jun 30, 2015
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A semiconductor structure containing a multiple threshold voltage III-V device is provided. The III-V device includes a III-V compound semiconductor core portion and a III-V compound semiconductor shell portion. The III-V compound semiconductor core and shell portions are virtually defect-free. The III-V compound semiconductor core portion of the III-V device is used for back-gating to achieve multiple threshold voltages. The III-V compound semiconductor shell portion of the III-V device is used as a channel material for a field effect transistor.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a fin stack of, from bottom to top, a III-V compound semiconductor material fin portion, an insulating III-V compound material fin portion and a topmost III-V compound semiconductor material fin portion extending upwards from a surface of a bulk silicon substrate, wherein a dielectric material structure is present on each sidewall surface of said fin stack and each dielectric material structure has a topmost surface that is vertically offset and located at, or beneath, a bottommost surface of said topmost III-V compound semiconductor material fin portion;
an insulating III-V compound layer straddling over a first portion of said topmost III-V compound semiconductor material fin portion;
a III-V compound semiconductor layer on said insulating III-V compound layer; and
a functional gate structure straddling over a portion of said III-V compound semiconductor layer, wherein a second portion of said topmost III-V compound semiconductor material fin portion is exposed.

2. The semiconductor structure of claim 1 , wherein said III-V compound semiconductor material fin portion comprises a lower portion having a first defect density and an upper portion having a second defect density that is lower than the first defect density.

3. The semiconductor structure of claim 2 , wherein defects within the lower portion of said III-V compound semiconductor material fin end at a sidewall surface of said dielectric material structure.

4. The semiconductor structure of claim 1 , further comprising a source region in a first portion of said III-V compound semiconductor layer and on one side of said functional gate structure, and a drain region in a second portion of said III-V compound semiconductor layer and on another side of said functional gate structure.

5. The semiconductor structure of claim 1 , wherein said insulating III-V compound layer directly contacts sidewall surfaces and a topmost surface of said first portion of said topmost III-V compound semiconductor material fin portion.

6. The semiconductor structure of claim 2 , wherein said insulating III-V compound material fin portion and said insulating III-V compound layer comprise a III-V material having a second band gap and said III-V compound semiconductor material fin portion, said topmost III-V compound semiconductor material fin portion and said III-V compound semiconductor layer comprise a III-V compound semiconductor material having a first band gap, wherein said second band gap is greater than said first band gap.

7. The semiconductor structure of claim 6 , wherein said insulating III-V compound material fin portion, said insulating III-V compound layer, said III-V compound semiconductor material fin portion, said topmost III-V compound semiconductor material fin portion and said III-V compound semiconductor layer have an epitaxial relationship and have said second defect density.

8. The semiconductor structure of claim 1 , wherein a portion of said insulating III-V compound layer and a portion of said III-V compound semiconductor layer contact said topmost surface of each dielectric material structure.

9. The semiconductor structure of claim 1 , wherein said second portion of said topmost III-V compound semiconductor material fin portion is a backgate.

10. The semiconductor structure of claim 1 , wherein said bulk silicon substrate has a {100} crystal orientation.

11. A method of forming a semiconductor structure, said method comprising:
providing a fin stack of, from bottom to top, a III-V compound semiconductor material fin portion, an insulating III-V compound material fin portion and a topmost III-V compound semiconductor material fin portion extending upwards from a surface of a bulk silicon substrate, wherein a dielectric material structure is present on each sidewall surface of said fin stack and each dielectric material structure has a topmost surface that is vertically offset and located at, or beneath, a bottommost surface of said topmost III-V compound semiconductor material fin portion;
forming an insulating III-V compound layer straddling over said topmost III-V compound semiconductor material fin portion;
forming a III-V compound semiconductor layer on said insulating III-V compound layer;
forming a gate structure straddling over a portion of said III-V compound semiconductor layer; and
exposing said topmost III-V compound semiconductor material fin portion at an end of said fin stack opposite an end containing said gate structure.

12. The method of claim 11 , wherein said providing said fin stack comprises:
forming a dielectric material layer on said surface of said bulk semiconductor substrate;
providing a trench in said dielectric material layer;
epitaxially growing a III-V compound semiconductor material fin within said trench;
recessing an upper portion of said III-V compound semiconductor material fin to provide said III-V compound semiconductor material fin portion;
epitaxially growing said insulating III-V compound material fin portion on a topmost surface of said III-V compound semiconductor material fin portion; and
epitaxially growing said topmost III-V compound semiconductor material fin portion on a topmost surface of said insulating III-V compound material fin.

13. The method of claim 12 , further comprising recessing remaining portions of said dielectric material layer to provide each dielectric material structure.

14. The method of claim 12 , wherein said III-V compound semiconductor material fin comprises a lower portion having a first defect density and an upper portion having a second defect density that is less than said first defect density.

15. The method of claim 11 , wherein said forming said insulating III-V compound layer comprises epitaxial growth.

16. The method of claim 11 , wherein said forming said III-V compound semiconductor layer comprises epitaxial growth.

17. The method of claim 11 , wherein said gate structure is a functional gate structure.

18. The method of claim 17 , further comprising forming a source region in a first portion of said III-V compound semiconductor layer and on one side of said functional gate structure, and forming a drain region in a second portion of said III-V compound semiconductor layer and on another side of said functional gate structure.

19. The method of claim 11 , wherein said gate structure is a sacrificial gate structure that is replaced with a functional gate structure after forming a source region in a first portion of said III-V compound semiconductor layer and on one side of said sacrificial gate structure, and forming a drain region in a second portion of said III-V compound semiconductor layer and on another side of said sacrificial gate structure.

20. The method of claim 11 , wherein said exposing said topmost III-V compound semiconductor material fin portion comprises etching said III-V compound semiconductor layer and said insulating III-V compound layer.

Assignees

• IBM
• Int Business Machines Corpoartion

Inventors

• Cheng Kangguo
• Fogel Keith E
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P14/3214

  being Group IIIA-VA semiconductors · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D62/405

  Orientations of crystalline planes · CPC title