Vertical transistor device with halo pocket contacting source

Patent metadata

Field	Value
Publication number	US-9496390-B2
Application number	US-201314024624-A
Country	US
Kind code	B2
Filing date	Sep 11, 2013
Priority date	Sep 11, 2013
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A vertical transistor device comprises a substrate, a first source, a drain, a first gate dielectric layer, a first gate electrode and a first doping region. The substrate has at least one protruding portion. The first source having a first conductivity type is formed on the substrate. The drain having the first conductivity type is disposed on the protruding portion. The first gate electrode is disposed adjacent to a first sidewall of the protruding portion. The first gate dielectric layer is disposed between the first gate electrode and the first sidewall as well as being disposed adjacent to the first source and the drain. The first doping region having a second conductivity type is formed beneath the protruding portion and adjacent to the first source.

First claim

What is claimed is:

1. A vertical transistor device comprising:
a substrate, having at least one protruding portion vertically protruding there from;
a first source, having a first conductivity type and formed on the substrate;
a drain, having the first conductivity type and disposed on the protruding portion;
a first gate electrode, disposed adjacent to a first sidewall of the protruding portion;
a first gate dielectric layer, disposed between the first gate electrode and the first sidewall of the protruding portion as well as disposed adjacent to the first source and the drain; and
a first doping region, having a second conductivity type and formed beneath the protruding portion and contacting the first source, wherein the protruding portion of the substrate in its entirety is overlapping the first doping region,
wherein the substrate has the second conductivity type, and the first doping region has a doping concentration greater than that of the substrate and less than that of the first source.

2. The vertical transistor device according to claim 1 , further comprising:
a second source, having the first conductivity type and formed on the substrate and adjacent to the first doping region;
a second gate electrode, disposed adjacent to a second sidewall of the protruding portion; and
a second gate dielectric layer, disposed between the second gate electrode and the second sidewall of the protruding portion as well as disposed adjacent to the second source and the drain.

3. The vertical transistor device according to claim 1 , wherein first doping region has a doping concentration of 1×10 13 cm −3 .

4. The vertical transistor device according to claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.

5. The vertical transistor device according to claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

6. The vertical transistor device according to claim 1 , wherein the protruding portion has a step height.

7. The vertical transistor device according to claim 1 , wherein the first doping region is a halo pocket structure.

Assignees

• United Microelectronics Corp

Inventors

• Su Hao
• Hu Hang
• Liao Hong

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10D64/0133

  at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D30/63 Primary

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H01L21/26586

  Electricity · mapped topic