Semiconductor devices with dummy gate structures partially on isolation regions

Patent metadata

Field	Value
Publication number	US-9496354-B2
Application number	US-201514812150-A
Country	US
Kind code	B2
Filing date	Jul 29, 2015
Priority date	May 1, 2014
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.

First claim

What is claimed:

1. A device, comprising:
an isolation region positioned in a semiconductor substrate that defines an active region in said semiconductor substrate;
a gate structure having a lateral width and opposing first and second sidewalls, wherein a first portion of said lateral width of said gate structure is positioned above and in direct contact with said isolation region and a second portion of said lateral width of said gate structure is positioned above said active region;
an L-shaped liner layer positioned on said isolation region and on and in direct contact with said first sidewall of said gate structure; and
a sidewall spacer positioned above said active region and on said second sidewall of said gate structure.

2. The device of claim 1 , wherein said sidewall spacer is a low-k spacer (k value less than 3.9).

3. The device of claim 2 , wherein said L-shaped liner layer is made of silicon nitride.

4. The device of claim 1 , further comprising a conductive contact structure positioned on said sidewall spacer.

5. The device of claim 4 , further comprising a layer of insulating material positioned on said L-shaped liner layer.

6. The device of claim 4 , wherein said conductive contact structure is a conductive trench silicide contact structure.

7. The device of claim 1 , wherein a thickness of said L-shaped liner on said first sidewall of said gate structure is less than a distance between said second sidewall of said gate structure and a nearest edge of an epi material formed on said active region.

8. The device of claim 1 , wherein the L-shaped liner layer is positioned on and in direct contact with said isolation region and the sidewall spacer is positioned on and in direct contact with said second sidewall of said gate structure.

9. A device, comprising:
an isolation region positioned in a semiconductor substrate that defines an active region in said semiconductor substrate;
a gate structure having a lateral width and opposing first and second sidewalls, wherein a first portion of said lateral width of said gate structure is positioned above and in direct contact with said isolation region and a second portion of said lateral width of said gate structure is positioned above said active region;
an L-shaped silicon nitride liner layer positioned on said isolation region and on and in direct contact with said first sidewall of said gate structure;
a low-k (k value less than 3.9) sidewall spacer positioned above said active region and on said second sidewall of said gate structure; and
a conductive contact structure positioned on said low-k sidewall spacer.

10. The device of claim 9 , further comprising a layer of insulating material positioned on said L-shaped liner layer.

11. The device of claim 10 , wherein said conductive contact structure is a conductive trench silicide contact structure.

12. The device of claim 9 , wherein a thickness of said L-shaped liner on said first sidewall of said gate structure is less than a distance between said second sidewall of said gate structure and a nearest edge of an epi material formed on said active region.

13. The device of claim 9 , wherein the L-shaped silicon nitride liner layer is positioned on and in direct contact with said isolation region and the low-k sidewall spacer is positioned on and in direct contact with said second sidewall of said gate structure.

14. A device, comprising:
an isolation region positioned in a semiconductor substrate that defines an active region in said semiconductor substrate;
a gate structure having a lateral width and opposing first and second sidewalls, wherein a first portion of said lateral width of said gate structure is positioned above and in direct contact with said isolation region and a second portion of said lateral width of said gate structure is positioned above said active region;
an epi material formed on said active region;
an L-shaped liner layer positioned on said isolation region and on and in direct contact with said first sidewall of said gate structure, wherein a thickness of said L-shaped liner on said first sidewall of said gate structure is less than a distance between said second sidewall of said gate structure and a nearest edge of said epi material formed on said active region;
a sidewall spacer positioned above said active region and on said second sidewall of said gate structure;
a conductive contact structure positioned on said sidewall spacer; and
a layer of insulating material positioned on said L-shaped liner layer.

15. The device of claim 14 , wherein said sidewall spacer is a low-k spacer (k value less than 3.9).

16. The device of claim 14 , wherein said L-shaped liner layer is made of silicon nitride.

17. The device of claim 14 , wherein said conductive contact structure is a conductive trench silicide contact structure.

18. The device of claim 14 , wherein the L-shaped liner layer is positioned on and in direct contact with said isolation region, the sidewall spacer is positioned on and in direct contact with said second sidewall of said gate structure and the conductive contact structure is positioned on and in direct contact with said sidewall spacer.

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Cai Xiuyu
• Jacob Ajey Poovannummoottil
• Knorr Andreas
• Prindle Christopher

Classifications

• H10P50/283

  by chemical means · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title