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Semiconductor device having vertical MOSFET with super junction structure, and method for manufacturing the same
US9496331B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9496331-B2 |
| Application number | US-201314649595-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 3, 2013 |
| Priority date | Dec 7, 2012 |
| Publication date | Nov 15, 2016 |
| Grant date | Nov 15, 2016 |
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Abstract
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A method for manufacturing a semiconductor device includes: preparing a semiconductor substrate, in which a first semiconductor layer is formed on a substrate; forming a first concave portion in the first semiconductor layer; forming trenches on the first semiconductor layer in the first concave portion; epitaxially growing a second semiconductor layer for embedding in each trench and the first concave portion; forming a SJ structure having PN columns including the second semiconductor layer in each trench and the first semiconductor layer between the trenches; and forming the vertical MOSFET by: forming a channel layer and a source region contacting the channel layer on the SJ structure; forming a gate electrode over the channel layer through a gate insulating film; forming a source electrode connected to the source region; and forming a drain electrode on a rear of the substrate.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method for manufacturing a semiconductor device having a vertical MOSFET with a super junction structure, comprising: preparing a semiconductor substrate, in which a first semiconductor layer having a first conductivity type is formed on a surface of a substrate made of a semiconductor material; forming a step in the first semiconductor layer by forming a first concave portion that includes at least a part of a main region of the first semiconducto…
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- H10P52/402Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9496331B2 cover?
- A method for manufacturing a semiconductor device includes: preparing a semiconductor substrate, in which a first semiconductor layer is formed on a substrate; forming a first concave portion in the first semiconductor layer; forming trenches on the first semiconductor layer in the first concave portion; epitaxially growing a second semiconductor layer for embedding in each trench and the first…
- Who is the assignee on this patent?
- Denso Corp
- What technology area does this patent fall under?
- Primary CPC classification H10P52/402. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 15 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).