Substrate resistor and method of making same

Patent metadata

Field	Value
Publication number	US-9496325-B2
Application number	US-201213533543-A
Country	US
Kind code	B2
Filing date	Jun 26, 2012
Priority date	Jun 26, 2012
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A semiconductor structure includes a resistor on a substrate formed substantially simultaneously with other device elements, such as one or more transistors. A diffusion barrier layer deposited on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor in a substantially similar manner as that used to form the gate of the transistor. The filler material is removed.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
forming a resistor over a substrate;
depositing a filler material over the resistor and the substrate;
patterning the filler material to be over a middle area of the resistor;
forming a first connector and a second connector over the resistor, wherein the first connector and the second connector are on opposing sides of the filler material; and
removing the filler material disposed between the first connector and the second connector, wherein the filler material is a different material layer than material forming the resistor.

2. The method of claim 1 further comprising:
forming a dielectric layer over the resistor, the first connector, and the second connector; and
forming contacts through the dielectric layer to the first connector and the second connector.

3. The method of claim 1 further comprising:
forming a diffusion barrier layer over the substrate, wherein the forming the diffusion barrier layer is performed by a same process at a same time as the forming the resistor over the substrate.

4. The method of claim 3 further comprising:
forming a first transistor gate over the diffusion barrier layer, wherein the forming the first transistor gate is performed by a same process and at a same time as the forming the first connector and the second connector over the resistor;
depositing a second transistor gate over the diffusion barrier layer, wherein the depositing the second transistor gate is performed by a same process and at a same time as the depositing a filler over the resistor and the substrate; and
patterning the second transistor gate, wherein the patterning the second transistor gate is performed by a same process and at a same time as the patterning the filler material.

5. The method of claim 1 , wherein the forming the resistor over the substrate includes:
forming an isolation region in the substrate; and
forming the resistor over the isolation region.

6. The method of claim 1 , wherein the forming the first connector and the second connector over the resistor includes:
depositing a metal layer over the resistor and the filler material; and
patterning the metal layer to be on the resistor and the sides of the filler material.

7. The method of claim 1 , wherein the depositing the filler material over the resistor includes depositing a doped polysilicon over the resistor.

8. The method of claim 1 , wherein the depositing the filler material over the resistor includes depositing a dielectric material over the resistor.

9. A method of forming a semiconductor structure, the method comprising:
forming an isolation region in a substrate;
forming a resistor over the isolation region;
depositing a filler material over the substrate, isolation region, and the resistor;
performing a first patterning of the filler material, wherein the filler material covers the resistor;
depositing a dielectric layer over the filler material, the isolation region, and the substrate;
performing a second patterning of the filler material, wherein the filler material covers a middle portion of the resistor;
forming a first connector on the resistor;
forming a second connector on the resistor; and
removing a portion of filler material disposed between the first connector and the second connector, wherein the filler material is a different material layer than material forming the resistor.

10. The method of claim 9 , wherein the removing the portion of filler material includes removing all of the filler material.

11. The method of claim 9 further comprising:
forming a diffusion barrier layer over the substrate and isolation region, wherein the forming the diffusion barrier layer is performed by a same process and at a same time as the forming the resistor over the isolation region.

12. The method of claim 11 , wherein the method further comprises forming a first transistor gate over the diffusion barrier layer, wherein the forming the first transistor gate is performed by a same process and at a same time as the forming the first connector on the resistor and the forming the second connector on the resistor.

13. The method of claim 12 further comprising:
depositing a second transistor gate over the diffusion barrier layer, wherein the depositing the second transistor gate is performed at the same time as the depositing a filler material over the substrate, isolation region, and the resistor; and
patterning the second transistor gate, wherein the patterning the second transistor gate is performed by a same process and at a same time as the performing the first patterning of the filler material.

14. The method of claim 9 , wherein the depositing the filler material includes depositing a doped polysilicon over the substrate, isolation region, and the resistor.

15. The method of claim 9 , wherein the depositing the filler material includes depositing a dielectric material over the substrate, isolation region, and the resistor.

16. A method of forming a semiconductor structure, the method comprising:
forming an isolation region in a substrate;
forming a gate dielectric layer over the substrate and the isolation region;
forming a diffusion barrier layer over the gate dielectric layer;
forming a polysilicon layer over the diffusion barrier layer;
patterning the polysilicon layer, the diffusion barrier layer, and the gate dielectric layer to form a first gate structure over the substrate, a resistor structure over the isolation region, and a patterned diffusion barrier layer over the isolation region;
forming sidewall spacers on the first gate structure;
forming sidewall spacers on the resistor structure;
patterning the first gate structure and the resistor structure to remove portions of the polysilicon layer between the sidewall spacers on the first gate structure and the resistor structure;
forming a metal gate electrode in the first gate structure, and forming a first connector and a second connector to a resistor in the resistor structure, the first connector being interposed between a portion of the polysilicon layer and a first one of the sidewall spacers on sidewalls of the resistor structure, the second connector being interposed between the portion of the polysilicon layer and a second one of the sidewall spacers on sidewalls of the resistor structure, the patterned diffusion barrier layer forming the resistor in the resistor structure, the resistor comprising a current path between the first connector and the second connector;
patterning the portion of the polysilicon layer on the resistor to form an opening between the first connector and the second connector, wherein material of the polysilicon layer on the resistor is a different material layer than material forming the resistor; and
forming a dielectric layer over the first gate structure and the resistor structure and in the opening between the first connector and the second connector.

17. The method of claim 16 further comprising:
forming a first metal contact through the dielectric layer to the metal gate electrode of the first gate structure; and
forming a second metal contact and a third metal contact through the dielectric layer to the first connector and the second connector, respectively, of the resistor structure.

18. The method of claim 16 , wherein the patterning the portion of the polysilicon layer on the resistor to form the opening between the first connector and the second connector includes removing all of the portion of the polysilicon layer on

Assignees

• Chen Hua Feng
• Wang Shu-Hui
• Chiang Mu-Chi
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hua Feng
• Wang Shu-Hui
• Chiang Mu-Chi

Classifications

• H10D84/817

  Combinations of field-effect devices and resistors only · CPC title

• H10D1/47 Primary

  Resistors having no potential barriers · CPC title

• H10D84/209

  of only resistors · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D64/664

  the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer · CPC title