Semiconductor memory device having lowered bit line resistance

Patent metadata

Field	Value
Publication number	US-9496275-B2
Application number	US-201414540803-A
Country	US
Kind code	B2
Filing date	Nov 13, 2014
Priority date	Jan 24, 2005
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device comprising:
forming an oxide/nitride/oxide (ONO) film on a semiconductor substrate;
forming, on the ONO film, an insulator mask layer having an opening corresponding to a bit line formation region;
selectively implanting an impurity ion in the semiconductor substrate with the insulator mask layer so as to form a first low-resistance layer;
etching the ONO film in the bit line formation region; and
forming a second low-resistance layer in contact with the first low-resistance layer in the bit line formation region and running in a direction in which a current flows, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer, and the second low-resistance layer having a top surface coplanar with a top surface of an oxide layer of the ONO film.

2. The method as claimed in claim 1 , wherein the step of forming the insulator mask layer comprises forming a space on a sidewall of the opening so that the opening is reduced.

3. The method as claimed in claim 1 , wherein the step of forming the insulator mask layer comprises the step of forming a silicon nitride layer as the insulator mask layer.

4. The method as claimed in claim 1 , further comprising:
removing an upper oxide layer of the ONO film prior to forming the second low-resistance layer; and
forming a silicon oxide layer on an exposed nitride layer of the ONO film and the second low-resistance layer exposed through the opening.

5. The method as claimed in claim 1 , wherein the step of forming the first low-resistance layer comprises selectively removing an upper oxide layer of the ONO film and an underlying nitride layer thereof in the bit line formation region before the impurity ion is implanted.

6. The method as claimed in claim 1 , wherein the step of forming the second low-resistance layer comprises forming a silicided metal layer.

7. The method as claimed in claim 6 , further comprising:
selectively providing resin on the silicided metal layer;
and removing the insulator mask.

8. The method as claimed in claim 1 , wherein the step of forming the second low-resistance layer comprises epitaxially growing a low-resistance silicon layer.

9. The method as claimed in claim 1 , wherein the step of forming the second low-resistance layer comprises forming the second low-resistance layer to a particular thickness for the top surface of the second low-resistance layer to be coplanar with the top surface of the oxide layer of the ONO film.

10. The method as claimed in claim 1 , wherein the step of forming the second low-resistance layer comprises:
epitaxially growing the second low-resistance layer to be higher than the top surface of the oxide layer of the ONO film; and
etching the second low-resistance layer to a particular thickness for the top surface of the second low-resistance layer to be coplanar with the top surface of the oxide layer of the ONO film.

Assignees

• Cypress Semiconductor Corp
• Monterey Res Llc

Inventors

• Kouketsu Hiroaki
• Hosaka Masaya

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P30/22

  using masks · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title