High mobility transistors

Patent metadata

Field	Value
Publication number	US-9496262-B2
Application number	US-201414572949-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	Dec 28, 2013
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

First claim

What is claimed is:

1. A method of forming an integrated circuit, comprising the steps:
providing a substrate comprising a semiconductor material extending to a top surface of said substrate, said semiconductor material comprising crystalline silicon;
forming a first hard mask over said substrate so as to expose said substrate in an area for a first polarity finFET and cover said substrate in an area for a second, opposite, polarity finFET;
forming a first polarity fin epitaxial layer comprising semiconductor material different from silicon over said substrate in said area exposed by said first hard mask;
removing said first hard mask, leaving said first polarity fin epitaxial layer in place;
forming a second hard mask over said substrate and said first polarity fin epitaxial layer so as to expose said substrate in said area for said second polarity finFET and cover said first polarity fin epitaxial layer in said area for said first polarity finFET;
forming a first buffer comprising germanium on said substrate in said area exposed by said second hard mask;
forming a second polarity fin epitaxial layer comprising semiconductor material different from silicon on said first buffer in said area exposed by said second hard mask;
removing said second hard mask, leaving said first polarity fin epitaxial layer and said second polarity fin epitaxial layer in place;
forming a fin mask over said first polarity fin epitaxial layer and said second polarity fin epitaxial layer which covers an area of said first polarity fin epitaxial layer for a first polarity fin and covers an area of said first polarity fin epitaxial layer for a second polarity fin;
removing semiconductor material from said second polarity fin epitaxial layer and said first polarity fin epitaxial layer in areas exposed by said fin mask to leave said second polarity fin and said first polarity fin;
removing said fin mask;
forming a layer of isolation dielectric material over said substrate, covering said second polarity fin and said first polarity fin;
planarizing said layer of isolation dielectric material down to said second polarity fin and said first polarity fin; and
recessing said layer of isolation dielectric material to provide an isolation dielectric layer of said integrated circuit, wherein said second polarity fin and said first polarity fin extend at least 10 nanometers above said isolation dielectric layer.

2. The method of claim 1 , further comprising forming a second buffer comprising germanium on said substrate in said area exposed by said first hard mask, prior to said step of forming said first polarity fin epitaxial layer, so that said first polarity fin epitaxial layer is formed on said second buffer.

3. The method of claim 1 , wherein said first polarity fin epitaxial layer is a p-channel fin epitaxial layer and comprises germanium.

4. The method of claim 1 , wherein said first polarity fin epitaxial layer is a p-channel fin epitaxial layer and comprises silicon-germanium with a germanium atomic fraction greater than 80 percent.

5. The method of claim 1 , wherein said second polarity fin epitaxial layer is an n-channel fin epitaxial layer and comprises gallium arsenide.

6. The method of claim 1 , wherein said second polarity fin epitaxial layer is an n-channel fin epitaxial layer and comprises indium gallium arsenide with an indium to gallium ratio of 50:50 to 57:43.

7. The method of claim 1 , wherein said second polarity fin epitaxial layer is an n-channel fin epitaxial layer and comprises indium phosphide.

8. The method of claim 1 , wherein said first buffer is formed so that a germanium atomic fraction of said first buffer is graded so that said germanium atomic fraction at a bottom surface of said first buffer is less than 20 percent and said germanium atomic fraction at a top surface of said first buffer is greater than 80 percent.

Assignees

• Texas Instruments Inc

Inventors

• Mehrotra Manoj
• Machala Iii Charles Frank
• Wise Rick L
• Niimi Hiroaki

Classifications

• H10P14/3421

  Arsenides · CPC title

• H10P14/3418

  Phosphides · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title