Semiconductor device

Patent metadata

Field	Value
Publication number	US-9496203-B2
Application number	US-201514727446-A
Country	US
Kind code	B2
Filing date	Jun 1, 2015
Priority date	Jul 31, 2013
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of transistor units including adjacent first, second and third transistor units arranged side by side in a first direction, each transistor unit having a plurality of transistors that are coupled to each other along a second direction intersecting the first direction;
a source wiring shared by adjacent first and second transistor units, the source wiring being coupled to each transistor in the adjacent first and second transistor units;
a drain wiring shared by adjacent second and third transistor units, the drain wiring being coupled to each transistor in the adjacent second and third transistor units;
a source pad electrode extending in the second direction and overlapping a portion of the source wiring via an insulating film, the source pad electrode being coupled to the source wiring; and
a drain pad electrode extending in the second direction and overlapping a portion of the drain wiring via an insulating film, the drain pad electrode being coupled to the drain wiring; wherein:
the source pad electrode and the drain pad electrode are arranged side by side in the first direction and do not overlap each other.

2. The semiconductor device according to claim 1 , further comprising:
a gate pad electrode extending in the second direction; and
a gate plate coupled to the gate pad electrode via a gate contact, the gate plate extending in the first direction.

3. The semiconductor device according to claim 2 , wherein:
the gate plate is coupled to a plurality of gate electrodes via a gate wiring; and
the plurality of gate electrodes have a comb-like shape.

4. The semiconductor device according to claim 3 , wherein:
the source pad electrode overlaps at least portions of said plurality of gate electrodes.

5. The semiconductor device according to claim 1 , wherein:
at least part of the source pad electrode overlaps a gate electrode of a plurality of the transistors.

6. The semiconductor device according to claim 1 ,
wherein each of the source and drain pad electrodes has a width in the second direction, which is larger than a width of the respective source and drain wirings, in said second direction.

7. The semiconductor device according to claim 1 ,
wherein bonding wires are joined to the source pad electrode and to the drain pad electrode at a plurality of points, the bonding wires being coupled to a terminal located on a lead frame of a semiconductor package.

Assignees

• Renesas Electronics Corp

Inventors

• Matsumoto Akira
• Miura Yoshinao
• Nakashiba Yasutaka

Classifications

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/534

  being rectangular · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title