Memory circuit

Patent metadata

Field	Value
Publication number	US-9496037-B2
Application number	US-201414546668-A
Country	US
Kind code	B2
Filing date	Nov 18, 2014
Priority date	May 18, 2012
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A memory circuit includes: a bistable circuit ( 30 ) that writes data; nonvolatile elements (MTJ 1 , MTJ 2 ) that store the data written in the bistable circuit into the nonvolataole element in a nonvolatile manner, and restore the data stored in a nonvolatile manner into the bistable circuit; and a determining unit ( 50 ) that does not store the data written in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is the same as the data in the nonvolatile elements, but stores the data in the bistable circuit into the nonvolatile elements when the data in the bistable circuit is not the same as the data in the nonvolatile elements.

First claim

The invention claimed is:

1. A memory circuit comprising:
a plurality of memory cells each including a bistable circuit configured to write data, and a nonvolatile element configured to store the data written in the bistable circuit in a nonvolatile manner and restore the data stored in a nonvolatile manner into the bistable circuit;
a control line connected to the nonvolatile element; and
a control unit configured to determine whether the data in the bistable circuit is the same as data in the nonvolatile element in each memory cell of the plurality of memory cells, the control unit not applying a voltage for storing the data written in the bistable circuit into the nonvolatile element to the control line when determining that the data in the bistable circuit is the same as the data in the nonvolatile element, the control unit applying the voltage for storing the data in the bistable circuit into the nonvolatile element to the control line when determining that the data in the bistable circuit is not the same as the data in the nonvolatile element.

2. The memory circuit according to claim 1 , wherein
the nonvolatile element stores the data in the bistable circuit by changing the resistance value thereof.

3. The memory circuit according to claim 1 , wherein
the nonvolatile element has one end connected to a node in the bistable circuit and has the other end connected to the control line, and
the control unit determines whether the data in the bistable circuit is the same as the data in the nonvolatile element based on a voltage of the control line when there is data written in the bistable circuit.

4. The memory circuit according to claim 3 , wherein
the bistable circuit includes a first node and a second node, the first node and the second node being complementary to each other, and
the nonvolatile element includes a first nonvolatile element and a second nonvolatile element, the first nonvolatile element having one end connected to the first node and the other end connected to the control line, the second nonvolatile element having one end connected to the second node and the other end connected to the control line.

5. The memory circuit according to claim 1 , wherein, when receiving a skip signal, the control unit does not determine whether the data in the bistable circuit is the same as the data in the nonvolatile element.

6. The memory circuit according to claim 1 , wherein the nonvolatile element is a ferromagnetic tunnel junction device.

7. A memory circuit comprising:
a plurality of memory cells each including a bistable circuit configured to write data, and a nonvolatile element configured to store the data written in the bistable circuit in a nonvolatile manner and restore the data stored in a nonvolatile manner into the bistable circuit;
a readout circuit configured to read out the data from the bistable circuit;
a control unit configured to determine whether the data in the bistable circuit is the same as data in the nonvolatile element in each memory cell of the plurality of memory cells, the control unit not storing the data written in the bistable circuit into the nonvolatile element when determining that the data in the bistable circuit is the same as the data in the nonvolatile element, the control unit storing the data in the bistable circuit into the nonvolatile element when determining that the data in the bistable circuit is not the same as the data in the nonvolatile element, wherein
the nonvolatile element has one end connected to a node in the bistable circuit and has the other end connected to a control line,
the control unit determines whether the data in the bistable circuit is the same as the data in the nonvolatile element based on an output of the readout circuit and the voltage of the control line.

8. The memory circuit according to claim 7 , wherein
the bistable circuit includes a first node and a second node, the first node and the second node being complementary to each other,
the control line includes a first control line and a second control line,
the nonvolatile element includes a first nonvolatile element and a second nonvolatile element, the first nonvolatile element having one end connected to the first node and the other end connected to the first control line, the second nonvolatile element having one end connected to the second node and the other end connected to the second control line, and
the control unit determines whether data in the first nonvolatile element and data in the second nonvolatile element contradict each other based on the output of the readout circuit and voltages of the first control line and the second control line.

9. A memory circuit comprising:
a plurality of cells each including a bistable circuit configured to write data, and a nonvolatile element configured to store the data written in the bistable circuit in a nonvolatile manner and restore the data stored in a nonvolatile manner into the bistable circuit, the cells being divided into a plurality of regions each including at least two of the cells; and
a control unit configured to determine whether the data in the bistable circuit in at least one of the cells included in a corresponding region has been rewritten in a volatile manner after data was last restored into the bistable circuit in each of the regions, the control unit not storing the data in the bistable circuits into the nonvolatile element in the cells included in the corresponding region when determining that the data in the bistable circuit has not been rewritten, the control unit storing the data in the bistable circuits into the nonvolatile element in the cells included in the corresponding region when determining that the data in the bistable circuit has been rewritten.

10. The memory circuit according to claim 9 , further comprising
a memory unit configured to store information as to whether the data in at least one of the bistable circuits has been rewritten, the memory unit being provided for each of the regions.

11. The memory circuit according to claim 9 , wherein, when receiving a skip signal, the control unit does not determine whether the data in the bistable circuits have been rewritten in a volatile manner after data was last restored into the bistable circuit.

12. A memory circuit comprising:
a ferromagnetic tunnel junction device;
a readout circuit configured to read out data that has already been properly written into the ferromagnetic tunnel junction device in a nonvolatile manner; and
a control unit configured not to write data to be written in a nonvolatile manner into the ferromagnetic tunnel junction device when an output of the readout circuit is the same as the data to be written into the ferromagnetic tunnel junction device in a nonvolatile manner, and configured to write the data to be written in a nonvolatile manner into the ferromagnetic tunnel junction device when the output of the readout circuit is not the same as the data to be written in a nonvolatile manner.

13. The memory circuit according to claim 12 , wherein the control unit determines whether the output of the readout circuit is the same as the data to be written into the ferromagnetic tunnel junction device in a nonvolatile manner, the control unit not writing the data to be written in a nonvolatile manner into the ferromagnetic tunnel junction device when determining that the output of the readout circuit is the same as the data to be written in a nonvolatile manner, the control unit writing the data to be written in a nonvolatile manner into the ferromagnetic tunnel junction device when determining that the output of the readout circuit is not the same as the data

Assignees

• Japan Science & Tech Agency

Inventors

• Yamamoto Shuichiro
• SHUTO Yusuke
• Sugahara Satoshi

Classifications

• G11C14/0081 Primary

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C2013/0076

  Write operation performed depending on read result · CPC title

• G11C14/0054

  in which the volatile element is a SRAM cell · CPC title