Method of reliably reading data stored in multi-level cell (MLC) non-volatile memory

Patent metadata

Field	Value
Publication number	US-9495518-B2
Application number	US-201213407333-A
Country	US
Kind code	B2
Filing date	Feb 28, 2012
Priority date	Feb 28, 2011
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

An apparatus and a method for reading from a non-volatile memory whereby soft decision data is used to determine the reliability of hard decision data. The hard decision data read from the non-volatile memory is de-randomized and the soft decision data read from the non-volatile memory is not de-randomized. Using the soft decision data, the hard decision data is decoded.

First claim

What is claimed is:

1. A method of operating a nonvolatile memory system, the method comprising:
reading randomized data stored at an address in a non-volatile memory using a first read voltage;
de-randomizing the randomized data using a random sequence generated by a random sequence generator, to generate de-randomized data;
performing soft decision read operation using a second read voltage and third read voltage, wherein the second read voltage and the third read voltage are different from the first read voltage and wherein the first read voltage is between the second read voltage and the third read voltage;
generating soft decision data indicating a reliability of the de-randomized data based on a result of the soft decision read operation; and
decoding the de-randomized data using the soft decision data.

2. The method of claim 1 , wherein the de-randomizing comprises:
combining the randomized data with a first random sequence;
combining the soft decision data with a second random sequence; and
outputting the de-randomized data and the soft decision data, and
wherein second random sequence is a sequence of only bit values of zero.

3. The method of claim 1 , further comprising:
controlling a switch configured to control a datapath in one of a first mode and a second mode,
wherein the switch is controlled to transmit the randomized data on a datapath to a de-randomizer in the first mode and bypass transmission of the soft decision data on the datapath to the de-randomizer in the second mode.

4. The method of claim 3 , wherein the de-randomizer comprises a logic gate configured to receive the random sequence and combine the random sequence with the randomized data to output de-randomized data in the first mode, and
wherein the soft decision data bypasses the logic gate in the second mode.

5. The method of claim 4 , wherein the logic gate is an exclusive-OR (XOR) logic gate.

6. The method of claim 5 , wherein the switch is configured to receive the randomized data and the soft decision data from a page buffer.

7. The method of claim 6 , further comprising:
outputting the de-randomized data and the soft decision data bypassing the logic gate to a buffer.

8. The method of claim 1 , further comprising:
inputting the randomized data and the read soft decision data to a page buffer,
and wherein the de-randomizing is performed at the page buffer based on the random sequence.

9. The method of claim 8 , wherein the random sequence is not received by the page buffer when the soft decision data is received by the page buffer.

10. The method of claim 8 , wherein the random sequence is received by the page buffer when the soft decision data is received by the page buffer, and
wherein the random sequence is not combined with the soft decision data at the page buffer.

11. The method of claim 1 , wherein the nonvolatile memory system comprises a controller and a flash memory, and
wherein the de-randomizing is performed by at least one of the controller and the flash memory.

12. The method of claim 1 , wherein the decoding uses low density parity check code.

13. A memory controller comprising:
a microprocessor;
a de-randomizer configured to receive a hard decision read command to de-randomize randomized data read from at an address in a non-volatile memory using a first read voltage according to a random sequence generated by a random sequence generator, and de-randomize the randomized data, in response to receiving the hard decision read command, under a control of the microprocessor; and
a decoder configured to decode the de-randomized data using soft decision data indicating a reliability of the de-randomized data generated using a second read voltage and a third read voltage, wherein the second read voila and the third read voltage are different from the first read voltage, and wherein the first read voltage is between the second read voltage and the third read voltage.

14. The memory controller of claim 13 , further comprising:
a switch configured to provide the randomized data along a datapath to the de-randomizer and to provide the soft decision data along a datapath that bypasses the de- randomizer.

15. The memory controller of claim 13 , wherein the de- randomizer is further configured to receive the randomized data and the soft decision data, and to combine the randomized data with a first random sequence and combine the soft decision data with a second random sequence, and
wherein second random sequence is a sequence of only bit values of zero.

16. The memory controller of claim 15 , wherein the de-randomizer comprises a plurality of linear feedback shift registers.

17. The memory controller of claim 13 , wherein the decoder uses low density parity check code.

18. A non-volatile memory system comprising the memory controller of claim 13 and a non-volatile memory configured to store the randomized data.

19. A non-volatile memory system comprising:
control logic; and
a non-volatile memory comprising:
a non-volatile memory cell array configured to store randomized data;
a page buffer configured to receive randomized data stored at an address in a non-volatile memory as a result of read data using a first read voltage and soft decision values as the results of read operation using a second read voltage and a third read voltage, from the non-volatile memory cell array, wherein the second read voltage and the third read voltage are different from the first read voltage, and wherein the first read voltage is between the second read voltage and the third read voltage;
a random sequence generator configured to generate a random sequence;
a multiplexer configured to receive the random sequence and output the random sequence;

wherein the page buffer is configured to de-randomize the first value of the randomized data based on the random sequence, output the de-randomized data, generate soft decision data indicating a reliability of the de-randomized data based on a result of soft decision values, and output the soft decision data.

20. The non-volatile memory system of claim 19 , wherein the multiplexer does not output the random sequence to the page buffer when the soft decision data is generated from the second values read from the non-volatile memory cell array.

21. The non-volatile memory system of claim 19 , wherein the page buffer comprises:
a plurality of latches,
wherein the multiplexer is configured to output the random sequence to the page buffer when the soft decision data is generated from the second values read from the non-volatile memory cell array, and
wherein the plurality of latches are configured so that an exclusive-OR (XOR) operation is not performed between the soft decision data and the random sequence.

Assignees

• Kim Yong June
• Son Hong Rak
• Kim Jae Hong
• Yoon Sang Yong
• Lee Ki Jun
• Chung Jung Soo
• Choi Seong Hyeog
• Samsung Electronics Co Ltd

Inventors

• Kim Yong June
• Son Hong Rak
• Kim Jae Hong
• Yoon Sang Yong
• Lee Ki Jun
• Chung Jung Soo
• Choi Seong Hyeog

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F12/14

  Protection against unauthorised use of memory {or access to memory} · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title