Processing system with low power wake-up pad

Patent metadata

Field	Value
Publication number	US-9494987-B2
Application number	US-201314093473-A
Country	US
Kind code	B2
Filing date	Nov 30, 2013
Priority date	Nov 30, 2013
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

An integrated circuit includes an input/output pad, an input circuit, and an output circuit. The input circuit is coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode. The output circuit is coupled to the input/output pad that provides output signals to the input/output pad. The output circuit includes a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal. The power supply terminal receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode. The well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.

First claim

What is claimed is:

1. An integrated circuit, comprising:
an input/output pad;
an input circuit coupled to the input/output pad that receives input signals including a wake-up signal that indicates when the integrated circuit is to switch from a power-down mode to an active mode; and
an output circuit coupled to the input/output pad that provides output signals to the input/output pad, wherein the output circuit comprises a first P channel transistor in a well having a drain coupled to the input/output pad, and a source coupled to a power supply terminal that receives a first power supply voltage during the active mode and is decoupled from any power supply during the power-down mode, wherein the well is coupled to the wake-up signal in response to the wake-up signal indicating a change from the power-down mode to the active mode.

2. The integrated circuit of claim 1 , wherein the integrated circuit further comprises an input for receiving a continuous voltage that is intended to be present during the power-down mode, wherein the continuous voltage is coupled to the input circuit during the power-down mode and the active mode.

3. The integrated circuit of claim 1 , wherein the output circuit further comprises a coupling circuit that couples the input/output pad to the well during the power-down mode.

4. The integrated circuit of claim 1 , wherein the output circuit further comprises a second P channel transistor having a source coupled to the input/output pad, a drain coupled to the well, and a gate coupled to the power supply terminal.

5. The integrated circuit of claim 4 , wherein the power supply terminal is coupled to ground during the power-down mode.

6. The integrated circuit of claim 5 , wherein the output circuit further comprises a third P channel transistor having a source connected to the power supply terminal, a drain connected to the well, and a gate configured to keep the third transistor non-conductive during the power-down mode and conductive during the active mode.

7. The integrated circuit of claim 6 , wherein the output circuit further comprises a first N channel transistor having a gate coupled to the power supply terminal, source coupled to ground, and drain connected to the gate of the third P channel transistor.

8. The integrated circuit of claim 7 wherein the output circuit further comprises a fourth P channel transistor having a gate coupled to the power supply terminal, a drain coupled to the gate of the third P channel transistor, and a source coupled to the input/output terminal.

9. The integrated circuit of claim 8 , wherein the output circuit further comprises an auto switch having input for receiving a logic signal and an output coupled to the gate of the first P channel transistor.

10. The integrated circuit of claim 6 , wherein the output circuit further comprises an inverter receiving power through the third P channel transistor.

11. The integrated circuit of claim 1 , further comprising a logic circuit coupled to the output circuit.

12. A method of operating an input/output circuit of an integrated circuit coupled to an input/output pad of the integrated circuit and having a power-down mode and an active mode, comprising:
supplying power to a first node during the active mode and removing power from the first node in response to switching from the active mode to the power-down mode;
coupling the first node to a well of a first P channel transistor having a drain coupled to the input/output pad during transition from the power-down mode to the active mode; and
coupling the input/output pad to the well during the power-down mode.

13. The method of claim 12 wherein the coupling the input/output pad to the well is further characterized by using a second P channel transistor coupled between the input/output pad and the well and having a gate coupled to the first node.

14. A method claim 13 , wherein the coupling the first node to the well is further characterized by using a third P channel transistor coupled between the well and the first node and causing the third P channel transistor to be conductive during the active mode.

15. The method of claim 14 , wherein the causing the third P channel transistor to be conductive during the active mode comprises coupling the gate of the third P channel transistor to ground during the active mode.

16. The method of claim 15 , wherein the coupling the gate of the third P channel transistor to ground during the active mode comprises using an N channel transistor coupled between ground and the gate of the third transistor and causing the N channel transistor to be conductive when the first node receives power.

17. The method of claim 16 further comprising providing an output to the input/output pad by coupling an output signal to a gate of the first P channel transistor during the active mode.

18. The method of claim 12 , wherein the coupling the input/output pad to the well during the power-down mode is further characterized as coupling a wake-up signal received at the input/output pad to the well during the power-down mode.

19. An integrated circuit having a power-down mode, an active mode, and an input/output pad for use in transferring data under the control of a central processing unit and for detecting a wake-up signal that directs the integrated circuit to switch from the power-down mode to the active mode, comprising;
an input circuit coupled to the input/output pad that receives input signals including the wake-up signal; and
an output circuit having a first P channel transistor ( 208 ) having a drain connected to the input/output circuit, a well, a gate, and a source coupled to a power supply terminal (OVDD) that provides power during the active mode and no power during the power-down mode, wherein the well is coupled to the power supply terminal during the active mode and to the input/output node during transition from the power-down mode to the active mode.

20. The integrated circuit of claim 19 , wherein the power supply terminal is grounded during the power-down mode and the wake-up signal is coupled to the well during the power-down mode.

Assignees

• Tran Dzung T
• Bhooshan Rishi
• Pandey Rakesh
• Takeda Fujio
• Freescale Semiconductor Inc

Inventors

• Tran Dzung T
• Bhooshan Rishi
• Pandey Rakesh
• Takeda Fujio

Classifications

• H10D30/6706

  for preventing leakage current  (TFTs characterised by the properties of the source or drain H10D30/6713) · CPC title

• H10D89/215

  comprising arrangements for charge pumping or biasing substrates · CPC title

• H10D62/103

  for increasing or controlling the breakdown voltage of reverse-biased devices · CPC title

• H01L29/0611

  Electricity · mapped topic

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title