Reset circuitry for integrated circuit

Patent metadata

Field	Value
Publication number	US-9494969-B2
Application number	US-201414457133-A
Country	US
Kind code	B2
Filing date	Aug 12, 2014
Priority date	Aug 12, 2014
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.

First claim

The invention claimed is:

1. Reset circuitry for an integrated circuit, wherein the integrated circuit is provided with a clock and a reset generator, the reset circuitry comprising:
a reset gating module for receiving a generated reset signal from the reset generator and for generating a clock gating instruction in response; and
a clock gating module, operably coupled to the reset gating module, for receiving the clock gating instruction and in response, for gating the clock and generating a confirmation signal when the clock has been gated,
wherein the reset gating module, upon receipt of the confirmation signal, releases the reset signal for propagation in the integrated circuit, and upon expiry of a first pre-set time period, instructs the clock gating module to re-instate the clock for at least a second pre-set time period.

2. The reset circuitry of claim 1 , wherein the integrated circuit is partitioned into domains and wherein the reset gating module comprises a plurality of reset gating circuits, each for receiving a respective reset signal from the reset generator for assertion and de-assertion in a respective domain.

3. The reset circuitry of claim 1 , wherein the first time period is no less than a maximum reset propagation delay of the integrated circuit.

4. The reset circuitry of claim 1 , wherein the second pre-set time period is no less than a minimum duration for which a reset procedure for the integrated circuit has to remain in a particular phase.

5. The reset circuitry of claim 1 , wherein the reset gating module compares a current operational status between itself and the reset generator and generates a control signal for application to the reset generator for synchronizing operation of the reset generator with itself.

6. The reset circuitry of claim 1 , wherein the integrated circuit has a plurality of clocks and wherein the clock gating circuit is arranged to:
detect a point in time when the clocks are in synchronism with one another; and
after receiving the clock gating instruction from the reset gating module, to delay gating the clocks until the clocks are detected to be in synchronism with one another.

7. The reset circuitry of claim 1 , further comprising a watchdog circuit for detecting a malfunction of the reset gating module or the clock gating module, and for generating one or more control signals for enabling a reset signal generated by the reset generator to be propagated within the integrated circuit.

8. The reset circuitry of claim 1 , wherein said reset circuitry is arranged to switch on a back-up clock on failure of the integrated circuit clock.

9. The reset circuitry of claim 1 , wherein said reset circuitry is arranged, upon failure of the integrated circuit clock, to switch in a bypass link so that a reset signal generated by the reset generator by-passes the reset gating module.

10. A method of resetting an integrated circuit, wherein the integrated circuit is provided with a clock and a reset generator, the method comprising:
detecting a generated reset signal and generating a clock gating instruction in response;
gating the clock and generating a confirmation signal when the clock has been gated;
releasing the reset signal for propagation in the integrated circuit; and
upon expiry of a first time period, re-instating the clock for at least a second time period.

11. An integrated circuit including reset circuitry, a reset generator and a clock, wherein the reset circuitry comprises:
a reset gating module for receiving a generated reset signal from the reset generator and for generating a clock gating instruction in response; and
a clock gating module, operably coupled to the reset gating module, for receiving the clock gating instruction and in response, for gating the clock and generating a confirmation signal when the clock has been gated,
wherein the reset gating module is arranged, on receipt of the confirmation signal, to release the reset signal for propagation in the integrated circuit, and on expiry of a first pre-set time period, to instruct the clock gating module to re-instate the clock for at least a second pre-set time period.

Assignees

• Gupta Aniruddha
• Pathak Akshay K
• Sharda Garima
• Sinha Nidhi
• Freescale Semiconductor Inc

Inventors

• Gupta Aniruddha
• Pathak Akshay K
• Sharda Garima
• Sinha Nidhi

Classifications

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/24

  Resetting means · CPC title