Solid imaging device including photoelectric conversion unit and TDI transfer unit

Patent metadata

Field	Value
Publication number	US-9491384-B2
Application number	US-201013258344-A
Country	US
Kind code	B2
Filing date	Mar 25, 2010
Priority date	Apr 1, 2009
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

In a solid-state imaging device 1 , an overflow gate (OFG) 5 has a predetermined electric resistance value, while voltage application units 16 1 to 16 5 are electrically connected to the OFG 5 at connecting parts 17 1 to 17 5 . Therefore, when voltage values V 1 to V 5 applied to the connecting parts 17 1 to 17 5 by the voltage application units 16 1 to 16 5 are adjusted, the OFG 5 can yield higher and lower voltage values in its earlier and later stage parts, respectively. As a result, the barrier level (potential) becomes lower and higher in the earlier and later stage parts, so that all the electric charges generated in an earlier stage side region of photoelectric conversion units 2 can be caused to flow out to an overflow drain (OFD) 4 , whereby only the electric charges generated in a later stage side region of the photoelectric conversion units 2 can be TDI-transferred.

First claim

The invention claimed is:

1. A solid-state imaging device comprising:
a photoelectric conversion unit, disposed along a predetermined direction, for generating an electric charge according to light incident thereon;
a TDI transfer unit for TDI-transferring the electric charge generated in the photoelectric conversion unit from an earlier stage side to a later stage side along the predetermined direction, the TDI transfer unit configured so as to operate on a plurality of pixels at the same time;
an overflow drain, disposed along the photoelectric conversion unit, including an overflow gate having a predetermined electric resistance value and earlier stage and later stage side parts; and
a voltage application unit electrically connected to apply voltage values to the overflow gate at a plurality of connecting parts of the overflow gate, wherein the voltage application unit is configured to adjust the voltage values applied to the plurality of connecting parts of the overflow gate, and the overflow gate is configured to respond to the voltage application unit adjusting the voltage values applied to the plurality of connecting parts of the overflow gate by yielding respectively higher and lower voltage values at the earlier stage and later stage side parts of the overflow gate.

2. A solid-state imaging device according to claim 1 , wherein the connecting parts are located at both end portions of the overflow gate in the predetermined direction and at an intermediate portion of the overflow gate in the predetermined direction; and
wherein the connecting part located at the intermediate portion is positioned at least on the later stage side of a center portion of the overflow gate in the predetermined direction.

3. A solid-state imaging device according to claim 1 , wherein gaps between adjacent connecting parts increase in narrowness towards the later stage side along the predetermined direction.

4. A solid-state imaging device according to claim 1 , wherein the voltage application unit changes the barrier level of the overflow gate by applying a voltage thereto such that all the electric charges generated in a predetermined region on the earlier stage side in the photoelectric conversion unit flow out to the overflow drain.

5. A solid-state imaging device according to claim 1 , wherein the voltage application unit applies voltage to the overflow gate such that a potential gradient occurring in the overflow gate gradually increases from the earlier stage side towards the later stage side.

6. A solid-state imaging device according to claim 1 , wherein, when the voltage application unit adjusts the voltage values applied to the plurality of connecting parts of the overflow gate, the overflow gate comprises a split resistance which causes the yielding of the respectively higher and lower voltage values at the earlier stage and later stage side parts of the overflow gate.

Assignees

• Suzuki Hisanori
• Yoneta Yasuhito
• Maeta Kentaro
• Muramatsu Masaharu
• Hamamatsu Photonics Kk

Inventors

• Suzuki Hisanori
• Yoneta Yasuhito
• Maeta Kentaro
• Muramatsu Masaharu

Classifications

• H04N25/622

  by controlling anti-blooming drains · CPC title

• H04N25/711 Primary

  Time delay and integration [TDI] registers; TDI shift registers · CPC title

• H10F39/158

  having arrangements for blooming suppression · CPC title

• H10F39/1538 Primary

  Time-delay and integration · CPC title

• H01L27/14831

  Electricity · mapped topic