Instruction for fast ZUC algorithm processing

Patent metadata

Field	Value
Publication number	US-9490971-B2
Application number	US-201213730230-A
Country	US
Kind code	B2
Filing date	Dec 28, 2012
Priority date	Dec 28, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Vector instructions for performing ZUC stream cipher operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first vector instruction to perform an update to a liner feedback shift register (LFSR), and receives a second vector instruction to perform an update to a state of a finite state machine (FSM), where the FSM receives inputs from re-ordered bits of the LFSR. The execution circuitry executes the first vector instruction and the second vector instruction in a single-instruction multiple data (SIMD) pipeline.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of vector registers; and
execution circuitry coupled to the plurality of vector registers, the execution circuitry operative to:
receive a first vector instruction to update a liner feedback shift register (LFSR) for stream cipher operations, wherein the first vector instruction specifies two or more of the plurality of vector registers as operands;
receive a second vector instruction to update a state of a finite st…

Assignees

• Intel Corp

Inventors

• Wolrich Gilbert M
• Gopal Vinodh
• Yap Kirk S
• Feghali Wajdi K

Classifications

• G09C1/00 Primary

  Physics · mapped topic

• H04L9/0662 Primary

  Electricity · mapped topic

• H04L2209/125

  Electricity · mapped topic

• G06F9/30036

  Physics · mapped topic

• G06F9/30038

  Physics · mapped topic