Simultaneous transmission of clock and bidirectional data over a communication channel

Patent metadata

Field	Value
Publication number	US-9490965-B2
Application number	US-201514731342-A
Country	US
Kind code	B2
Filing date	Jun 4, 2015
Priority date	Jun 12, 2012
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Embodiments of the invention are generally directed to simultaneous transmission of clock and bidirectional data over a communication channel. An embodiment of a transmitting device includes a modulator to generate a modulated signal including a clock signal and a data signal, the clock signal being modulated by a first signal edge of the modulated signal and the data signal being modulated by a position of a second signal edge of the modulated signal; a driver to drive the modulated signal on a communication channel; an echo canceller to subtract reflected signals on the communication channel; and a data recovery module to recover a signal received on the communication channel, the received signal being encoded by Return-to-Zero (RZ) encoding, the signal being received simultaneously with driving the modulated signal on the communication channel.

First claim

What is claimed is:

1. A device comprising:
an edge detector to extract a clock signal from a first edge of a signal received on a communication channel;
a data recovery circuit to recover a data signal from the received signal, the data signal being modulated by a position of a second edge of the received signal;
a encoder to encode a signal for transmission, the encoder to encode the signal using Return-to-Zero (RZ) encoding; and
a driver to drive the encoded signal on the communication channel, the encoded signal being driven simultaneously with receipt of the received signal.

2. The device of claim 1 , wherein the communication channel is a single wire channel.

3. The device of claim 1 , wherein the communication channel is a differential pair channel.

4. The device of claim 1 , wherein the modulation of the received signal includes a first value being encoded by a signal edge at a first position and a second value being encoded by a signal edge at a second position, wherein the second position is a later signal edge position than the first position.

5. The device of claim 1 , wherein the encoded signal is driven at a phase that avoids a time that matches a rising edge of the received signal in order to preserve a rising clock edge for the clock signal in the received signal.

6. The device of claim 1 , wherein the encoded signal is delayed a certain period of time in relation to the clock signal.

7. The device of claim 1 , further comprising an echo canceller to cancel echo on the communication channel, the data recovery circuit to recover the data signal from an output signal of the echo canceller.

8. The device of claim 1 , wherein the clock signal is a reference for data on a second communication channel.

9. The device of claim 1 , wherein the clock signal is a multiple of video clock of a second communication channel.

10. The device of claim 8 , wherein the clock signal is the reference for transition minimized differential signaling (TMDS) data on the second communication channel.

11. A method comprising:
encoding a signal for transmission with Return-to-Zero encoding, and
driving the encoded signal on a communication channel;
receiving a signal on the communication channel simultaneously with driving the encoded signal on the communication channel;
detecting a first edge of the received signal to extract a clock signal;
recovering a data signal from the received signal, the data signal being modulated by a position of a second signal edge of the received signal.

12. The method of claim 11 , wherein the encoded signal is driven on a single wire channel and the received signal is received on the single wire channel.

13. The method of claim 11 , wherein the encoded signal is driven on a differential pair channel and the received signal is received on the differential pair channel.

14. The method of claim 11 , wherein the encoded signal is driven at a phase that avoids a time that matches a rising edge of the received signal in order to preserve a rising clock edge for the clock signal in the received signal.

15. The method of claim 11 , further comprising delaying transmission of the encoded signal a certain period of time in relation to the extracted clock signal.

16. The method of claim 11 , wherein the modulation of the received signal includes a first value being encoded by a signal edge at a first position and a second value being encoded by a signal edge at a second position, wherein the second position is a later signal edge position than the first position.

17. The method of claim 11 , further comprising cancelling signal echo on the communication channel based on the encoded signal.

18. The method of claim 11 , further comprising applying the clock signal as a reference for a second communication channel.

19. The method of claim 11 , wherein the clock signal is a multiple of video clock of a second communication channel.

20. The method of claim 18 , wherein the clock signal is applied as the reference for transition minimized differential signaling (TMDS) data on the second communication channel.

Assignees

• Lattice Semiconductor Corp

Inventors

• Lee Inyeol
• Sung Baegin
• Sohn Hanwoong
• Tahk Shinje
• Baek Sun Woo
• Harrell Chandlee B

Classifications

• H04B7/015 Primary

  Reducing echo effects · CPC title

• H04L7/0278

  Band edge detection · CPC title

• H04L25/493

  by transition coding, i.e. the time-position or direction of a transition being encoded before transmission · CPC title

• H04L7/042

  Detectors therefor, e.g. correlators, state machines (digital correlators in general G06F17/15) · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title