Apparatus and methods for tuning a voltage controlled oscillator

Patent metadata

Field	Value
Publication number	US-9490827-B2
Application number	US-201514697465-A
Country	US
Kind code	B2
Filing date	Apr 27, 2015
Priority date	Nov 4, 2005
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.

First claim

What is claimed is:

1. An apparatus comprising:
a prescaler circuit configured to receive a voltage controlled oscillator (VCO) output signal from a VCO and to generate a divided signal based on the VCO output signal;
a counter module configured to generate, based on the divided signal, a feedback signal to be used for fine tuning the VCO in a fine tuning mode; and
a digital processing logic circuit configured to receive the divided signal and a reference clock signal, to count a number of cycles of the divided signal that occur during a calibration interval having a duration that is about equal to a division ratio Q of the digital processing logic circuit divided by a frequency of the reference clock signal, and to set a value of a capacitor array control signal based on the number of cycles of the divided signal to cause the VCO output signal to reach a coarse tuning target frequency in a coarse tuning mode.

2. The apparatus of claim 1 wherein the digital processing logic circuit is further configured to set the value of the capacitor array control signal to an initial value, the capacitor array control signal including a plurality of bits.

3. The apparatus of claim 2 wherein the digital processing logic circuit is further configured to determine a final value of a first bit of the capacitor array control signal based on comparing the number of cycles counted to a product of a division control signal M and a division ratio Q when the capacitor array control signal is set to the initial value.

4. The apparatus of claim 1 wherein the number of cycles counted is approximately equal to a product of a division control signal M and a division ratio Q when the digital processing logic circuit has set the capacitor array control signal to a final value.

5. The apparatus of claim 1 wherein the prescaler circuit has a selectable division ratio, the counter module further configured to control a value of the selectable division ratio to be one of a first integer division value P or a second integer division value P+1, the first integer division value P about equal to a division ratio Q of the digital processing logic circuit.

6. A phase-locked loop (PLL) comprising:
a capacitor array including a plurality capacitors digitally selectable by a capacitor array control signal;
a voltage controlled oscillator (VCO) having a voltage input and configured to generate a VCO output signal, a frequency of the VCO output signal based on a voltage level at the voltage input and on a value of the capacitor array control signal;
a prescaler circuit configured to receive the VCO output signal and to generate a divided signal based on the VCO output signal;
a counter module configured to generate, based on the divided signal, a feedback signal to be used for fine tuning the VCO in a fine tuning mode; and
a digital processing logic circuit configured to receive the divided signal and a reference clock signal, to count a number of cycles of the divided signal that occur during a calibration interval having a duration that is about equal to a division ratio Q of the digital processing logic circuit divided by a frequency of the reference clock signal, and to set the value of the capacitor array control signal based on the number of cycles of the divided signal to cause the VCO output signal to reach a coarse tuning target frequency in a coarse tuning mode.

7. The PLL of claim 6 wherein the digital processing logic circuit is further configured to generate a tuning control signal to configure the PLL between the fine tuning mode and the coarse tuning mode, the prescaler circuit configured to operate in both the fine tuning and coarse tuning modes, the digital processing logic circuit configured to operate in the coarse tuning mode.

8. The PLL of claim 7 wherein the VCO is configured to receive a reference voltage during the coarse tuning mode, the reference voltage proportional to temperature.

9. The PLL of claim 6 further comprising a phase-frequency detector (PFD) and charge pump module configured to receive the feedback signal and a reference clock signal, the PFD and charge pump module configured to generate a correction signal based on the feedback signal and the reference clock signal.

10. The PLL of claim 6 wherein the digital processing logic circuit is further configured to set the value of the capacitor array control signal to an initial value, the capacitor array control signal including a plurality of bits.

11. A phase-locked loop (PLL) comprising:
a capacitor array including a plurality capacitors digitally selectable by a capacitor array control signal including a plurality of bits;
a voltage controlled oscillator (VCO) having a voltage input and configured to generate a VCO output signal, a frequency of the VCO output signal based on a voltage level at the voltage input and on a value of the capacitor array control signal;
a prescaler circuit configured to receive the VCO output signal and to generate a divided signal based on the VCO output signal;
a counter module configured to generate, based on the divided signal, a feedback signal to be used for fine tuning the VCO in a fine tuning mode; and
a digital processing logic circuit configured to receive the divided signal, to count a number of cycles of the divided signal that occur during a calibration interval, and to set the value of the capacitor array control signal based on the divided signal to cause the VCO output signal to reach a coarse tuning target frequency in a coarse tuning mode, the digital processing logic circuit configured to set the value of the capacitor array control signal by setting the value of the capacitor array control signal to an initial value and determining a final value of a first bit of the capacitor array control signal based on comparing the number of cycles counted to a product of a division control signal M and a division ratio Q when the capacitor array control signal is set to the initial value.

12. A phase-locked loop (PLL) comprising:
a capacitor array including a plurality capacitors digitally selectable by a capacitor array control signal;
a voltage controlled oscillator (VCO) having a voltage input and configured to generate a VCO output signal, a frequency of the VCO output signal based on a voltage level at the voltage input and on a value of the capacitor array control signal;
a prescaler circuit configured to receive the VCO output signal and to generate a divided signal based on the VCO output signal, the prescaler circuit having a selectable division ratio;
a counter module configured to generate, based on the divided signal, a feedback signal to be used for fine tuning the VCO in a fine tuning mode, and to control a value of the selectable ratio to be one of a first integer division value P and a second integer division value P+1; and
a digital processing logic circuit configured to receive the divided signal and to set the value of the capacitor array control signal based on the divided signal to cause the VCO output signal to reach a coarse tuning target frequency in a coarse tuning mode, the first integer division value P about equal to a division ratio Q of the digital processing logic circuit.

13. A method of tuning a phase-locked loop (PLL), the method comprising:
generating a voltage controlled oscillator (VCO) output signal using a VCO coupled to a capacitor array, a frequency of the VCO output signal based on an input voltage of the VCO and on a value of a capacitor array control signal of the capacitor array;
dividing the VCO output signal to generate a divided signal using a prescaler circuit;
counting a number of cycles of the divided signal

Assignees

• Skyworks Solutions Inc

Inventors

• Wang Hua
• Ripley David Steven
• Roll Bryan J

Classifications

• H03L7/187

  using means for coarse tuning the voltage controlled oscillator of the loop (H03L7/191 - H03L7/195 take precedence) · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/0992 Primary

  comprising a counter or a frequency divider · CPC title

• H03L7/10 Primary

  for assuring initial synchronisation or for broadening the capture range · CPC title

• H03L7/193

  the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider · CPC title