High-speed level-shifting multiplexer

Patent metadata

Field	Value
Publication number	US-9490813-B2
Application number	US-201414534967-A
Country	US
Kind code	B2
Filing date	Nov 6, 2014
Priority date	Nov 6, 2014
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.

First claim

What is claimed is:

1. A level-shifting multiplexer, comprising:
a first pull-down circuit coupled to a first node and having first and second branches, wherein the first pull-down circuit is configured to pull-down the first node via the first branch in response to a first input driven to a first state and a first select signal being at a second state, and configured to pull down the first node via the second branch in response to a second input driven to a third state and a second select signal being at a fourth state;
a second pull-down circuit coupled to a second node and having third and fourth branches, wherein the second pull-down circuit is configured to pull-down the second node via the third branch in response to a third input driven to a fifth state and the first select signal being at the second state, and configured to pull down the second node via the fourth branch in response to a fourth input driven to a sixth state and the second select signal being at the fourth state; and
a pull-up circuit configured to pull up the first node if the second node is pulled down by the second pull-down circuit, and to pull up the second node if the first node is pulled down by the first pull-down circuit.

2. The level-shifting multiplexer of claim 1 , wherein each of the first, third, fifth, and sixth states is a logic one state.

3. The level-shifting multiplexer of claim 2 , wherein the first and third inputs are driven by a first pair of complementary signals, and the second and fourth inputs are driven by a second pair of complementary signals.

4. The level-shifting multiplexer of claim 1 , wherein the pull-up circuit comprises:
a first transistor configured to pull up the first node if the second node is pulled down by the second pull-down circuit, wherein the first transistor has a gate coupled to the second node; and
a second transistor configured to pull up the second node if the first node is pulled down by the first pull-down circuit, wherein the second transistor has a gate coupled to the first node.

5. The level-shifting multiplexer of claim 4 , wherein the first and second transistors comprise cross-coupled p-type metal-oxide-semiconductor (PMOS) transistors.

6. The level-shifting multiplexer of claim 4 , further comprising a choke circuit configured to reduce current from a supply rail to the first transistor if the first input is driven to the first state and the first select signal is at the second state.

7. The level-shifting multiplexer of claim 6 , wherein the choke circuit is configured to reduce current from the supply rail to the first transistor if the second input is driven to the third state and the second select signal is at the fourth state.

8. The level-shifting multiplexer of claim 6 , wherein the choke circuit is configured to reduce current from the supply rail to the second transistor if the third input is driven to the fifth state and the first select signal is at the second state.

9. The level-shifting multiplexer of claim 1 , further comprising a clamp transistor coupled between the second node and a ground, wherein the clamp transistor is configured to turn on if a disable signal is in a logic one state.

10. The level-shifting multiplexer of claim 1 , wherein:
the first branch comprises first and second transistors coupled in series between the first node and ground, wherein the first transistor includes a control terminal configured to receive the first select signal, and wherein the first input comprises a control terminal of the second transistor;
the second branch comprises third and fourth transistors coupled in series between the first node and ground, wherein the third transistor includes a control terminal configured to receive the second select signal, and wherein the second input comprises a control terminal of the fourth transistor;
the third branch comprises fifth and sixth transistors coupled in series between the second node and ground, wherein the fifth transistor includes a control terminal configured to receive the first select signal, and wherein the third input comprises a control terminal of the sixth transistor; and
the fourth branch comprises seventh and eighth transistors coupled in series between the second node and ground, wherein the seventh transistor includes a control terminal configured to receive the second select signal, and wherein the fourth input comprises a control terminal of the eighth transistor.

11. The level-shifting multiplexer of claim 1 , wherein the first and second select signals are complementary signals.

12. A method for level-shifting multiplexing, comprising:
receiving first and second select signals;
receiving first, second, third, and fourth input signals;
pulling down a first node via a first branch based on the first select signal and the first input signal;
pulling down the first node via a second branch based on the second select signal and the second input signal;
pulling down a second node via a third branch based on the first select signal and the third input signal;
pulling down the second node via a fourth branch based on the second select signal and the fourth input signal;
pulling up the first node if the second node is pulled down; and
pulling up the second node if the first node is pulled down.

13. The method of claim 12 , wherein each of the first and third input signals, and the second and fourth input signals comprises a differential input signal.

14. The method of claim 13 , wherein pulling up the first node if the second node is pulled down comprises pulling up the first node to a first voltage, wherein the first and third input signals or the second and fourth input signals comprises a differential signal having a voltage swing approximately equal to a second voltage and the first voltage is greater than the second voltage.

15. The method of claim 12 , wherein pulling up the first node if the second node is pulled down comprises pulling up the first node using a first transistor coupled between a supply rail and the first node, and pulling up the second node if the first node is pulled down comprises pulling up the second node using a second transistor coupled between the supply rail and the second node.

16. The method of claim 15 , further comprising choking current from the supply rail to the first transistor if the first node is pulled down.

17. The method of claim 16 , further comprising choking current from the supply rail to the second transistor if the second node is pulled down.

18. The method of claim 12 , wherein:
the first branch comprises first and second transistors coupled in series between the first node and ground, and wherein pulling down the first node via the first branch comprises applying the first select signal and the first input signal to control terminals of the first and second transistors, respectively;
the second branch comprises third and fourth transistors coupled in series between the first node and ground, and wherein pulling down the first node via the second branch comprises applying the second select signal and the second input signal to control terminals of the third and fourth transistors, respectively;
the third branch comprises fifth and sixth transistors coupled in series between the second node and ground, and wherein pulling down the second node via the third branch comprises applying the first select signal and the third input signal to control terminals of the fifth and sixth transistors, respectively; and
the fourth branch comprises seventh and eighth transistors coupled in series between the s

Assignees

• Qualcomm Inc

Inventors

• Bowles Kevin Robert
• Corona Jose Gabriel
• Boynapalli Venugopal

Classifications

• H03K19/018507 Primary

  Interface arrangements · CPC title

• H03K3/35613 Primary

  the input circuit having a differential configuration · CPC title

• H03K17/002

  Switching arrangements with several input- or output terminals (code converters H03M5/00, H03M7/00) · CPC title

• H03K17/005

  with several inputs only · CPC title

• H03K19/018528 Primary

  with at least one differential stage · CPC title